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98 SMT007 MAGAZINE I JULY 2019 wire bonds. The dimension of nodules, includ- ing height, and the size of scratches, includ- ing width, were measured before wire bonding. Wire bonding was then performed directly on various sizes of nodules and scratches on the bonding pad, and the evaluation of wire bonds was conducted using wire pull tests before and after reliability testing. Based on the results of the wire-bonding evaluation, the internal spec - ification for nodules and scratches for wire- bondable PCBs was modified to allow nodules and scratches with a certain height and a width limitation compared to initially adopted internal specifications of no nodules and no scratches. Such an approach resulted in improved yield at the PCB manufacturer. Introduction The development of the chip-on-board (COB) type of image sensors has significantly increased in the last few years to accommo- date an increasing demand for low-cost, high- performance industrial inspection cameras. Wire bonding is the most commonly used technology for making the electrical intercon - nection between a silicon image sensor and its substrate during image sensor fabrication. Therefore, wire bonding directly on the PCB surface is inevitable for COB-type image sen - sor fabrication. IPC-A-600J section—surface plating, wire-bond pads [1] —states, "Wire-bond pads are free of surface nodules, roughness, electrical test witness marks or scratches that exceed 0.8 mm (32 min) RMS (root-mean-square) in the pristine area in accordance with an applicable test method AABUS." Since the tolerance of sur - face nodules (<0.8 mm RMS) in IPC-A-600J for wire bonding pads is not easily measurable and may not properly reflect single nodules and shallow scratches, the initially adopted specification for wire bonding pads as a user was defined to be free of surface nodules and scratches. Therefore, a board was considered a reject if a nodule or a scratch was visible in the pristine area of the wire-bond at 20X magni- fication. If in any doubt, one could use 40X magnification for inspection to clarify pass/fail. However, in reality, it was difficult to achieve a wire-bonding surface in specification without nodules or scratches, resulting in low yield at the PCB manufacturer. In particular, PCB prod- ucts designed with a center cut-out slot close to bonding pads were prone to significant yield loss due to nodules. Yield review with the manufacturer and the analysis of causes for rejects using Pareto charts pointed out that two main reasons for PCB rejects were due to nodules and scratches on the wire-bonding surface. Yield had been reviewed on a monthly basis for 28 months, and the major yield losses continued to be due to nodules and scratches on the wire-bonding surface during the period. Figure 1 shows the Figure 1: Average yield loss from multiple wire-bonding PCB products.

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