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48 DESIGN007 MAGAZINE I AUGUST 2019 At DC and low frequencies, the inductance of transmission line paths can be ignored. However, as the frequency and rise time in- crease, we soon realize that the multilayer PCB is not an ideal environment to transfer high- speed data. Here, parasitic capacitance and in- ductance plague the most basic of designs. In- ductance, in particular, impacts on virtually all signal and power integrity issues. To optimize the physical layout for accept- able performance, inductance must be mini- mized: 1. The mutual inductance between signal paths intensifies switching noise 2. The inductance of the power distribution network (PDN) bypass and decoupling capacitors dramatically affects product performance and reliability 3. The effective loop inductance of the return current paths impacts on electromagnetic (EM) emissions By understanding how the physical PCB layout influences the degree of inductance, the PCB designer can triumph over their arch- enemy. Electric fields and magnetic fields play an equal role in moving energy in a multilayer PCB. EM fields also move energy in free space but not at DC. The presence of voltage implies that there is an electric field, and the changing of that electric field creates a magnetic field. What may not be appreciated is that moving a voltage between two components requires moving energy (not a signal), which requires the existence of both electric and magnetic fields. When energy is not moving, the mag- netic field is zero. 1. Mutual Inductance Between Signal Paths When current flows in a conductor, there is a magnetic field. When a second conductor, car- rying current, is brought into close proximity, there is a force between the two. If both cur- The Curse of the Golden Board Beyond Design by Barry Olney, IN-CIRCUIT DESIGN PTY LTD / AUSTRALIA

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