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70 DESIGN007 MAGAZINE I AUGUST 2019 Article by Chang Fei Yee KEYSIGHT TECHNOLOGIES This article will discuss the effect of decou- pling capacitors upon a PCB's power and signal integrity. The study was performed with post- layout co-simulation of power and signal in- tegrity to analyze power distribution network impedance, simultaneous switching noise, and eye diagrams. Introduction It is crucial for hardware designers to iden- tify the resonant frequency of each element (e.g., bypass/decoupling capacitor, planar ca- pacitance, and interconnect inductance) of the power distribution network (PDN) on a PCB and its impact on power integrity. A PCB with poor power integrity—such as a higher-than- targeted PDN impedance across the wide- band range—results in simultaneous switch- ing noise (SSN) and a shrunken eye diagram of the signal transmitted by the IC that draws power from the PDN. This article demonstrates the post-layout co-simulation of power and sig- nal integrity using Mentor HyperLynx to ana- lyze the impact of decoupling capacitors upon PDN impedance, SSN, and eye diagrams. Analysis and Results A PCB containing a system-on-a-chip (SoC) with DDR4 memory interface is laid out. In Figure 1a, the PDN named 1.2V on lay- er 4 supplies power to a memory interface that consists of one memory IC highlighted in blue. Meanwhile, the ground or reference plane, highlighted in green, is laid out on lay - er 5. The memory IC has 13 BGA power pins. The footprint of the 0.22-uF Decoupling Capacitors' Impact on Power and Signal Integrity Figure 1a: Top view of the 1.2V power rail supplying power to the DDR4 memory interface.

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