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72 DESIGN007 MAGAZINE I AUGUST 2019 decoupling capacitor (highlighted in brown) in a 0201 package dimension is placed across each of the power pins and the ground. Ad- ditionally, the footprint of bypass capacitors, 10 uF and a 1 uF respectively (highlighted in brown as well), is placed across the 1.2V pow- er net and ground. The eight data signals of this memory interface are shown in Figure 1b. To study the impact of a decoupling capaci- tor on PDN impedance, SSN, and eye diagrams, post-layout co-simulation of power and sig- nal integrity in HyperLynx is performed with PDN conditions listed in Table 1. Each PDN condition has the same PCB layout and stack- up depicted in Figure 1a and 1b loaded with one 10uF and one 1uF bypass capacitor. In condition A, there is no 0.22-uF decoupling capaci- tor. In B, there are four 0.22- uF capacitors. In C, the num- ber of 0.22-uF capacitors is increased to eight. Mean- while, in D, the quantity of 0.22-uF capacitors is further increased to 13. Subsequently, the pow- er-aware IBIS v5.0 model of memory IC and SoC, respec- tively, is imported into the software tool. Memory read operation at 1 Gbps, 500M Hz Nyquist frequency, is set for the mode of co- simulation, whereby the data bus is driven by the memory IC, and the SoC serves as the re- ceiving end (Rx). First, the PDN impedance that spans from 1,000 Hz to 2 GHz for the four PDN conditions is compared. In theory, the resonant frequen- cy is inversely proportional to the capacitance. With reference to Figure 2, all four PDN con- ditions have the same impedance profile from 1,000 Hz up to 10 MHz due to the placement of the same number of 10-uF and 1-uF bypass capacitors. Contrast PDN condition A (with no 0.22-uF decoupling capacitors) with conditions B, C, and D (each with at least four 0.22-uF de- coupling capacitors) and note the decrease in Figure 1b: The eight data signals of the DDR4 memory interface. Table 1: PDN conditions being studied. Figure 2: Simulated PDN impedance plots.

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