Issue link: https://iconnect007.uberflip.com/i/1153097
AUGUST 2019 I DESIGN007 MAGAZINE 51 that is equal to its ESR. Then, a sufficient num- ber of those capacitors are placed in parallel so that the accumulated ESR's approach the de- sired target impedance. In addition, the mounting inductance of a capacitor is comprised of three components: capacitor footprint, capacitor height above or below the plane, and power plane spreading inductance. These three elements describe the loop that current must flow; the bigger the loop, the more the inductance. The footprint (land pattern) for a capacitor dominates the ESL. It consists of via placement with respect to the pad, the length and width of traces connected to the pad, and the way the vias are connected to the power and ground planes. The location of the power/ground planes in the PCB stack- up controls the length of the vias; this is why it is always best to place the decoupling capaci- tors on the same side of the board as the BGA for high layer-count stackups. Inductance di- rectly depends on the magnetic field, so reduc- ing the energy associated with the loop area re- duces overall inductance. Figure 3 illustrates 0402 capacitors with dif- ferent fanout patterns. End vias are the worst case where the loop area (inductance) is the largest. This loop area can be reduced by plac- ing the vias closer to the land side and even more so by placing double vias either side of the pad basically halving the inductance. The final case is that of via-in-pad, which reduces the loop area dramatically, but caution should be used as not all assembly shops support this. Placing double vias has approximately the same inductance as using the via-in-pad. Also, vias should be directly connected to the plane rather than by thermal reliefs, which adds to the inductance. 3. Loop Inductance of the Return Paths PCB designers, generally, take great care to ensure that critical signals are routed exactly to Figure 2: A capacitor has series capacitance, resistance, and inductance (iCD PDN Planner). Figure 3: Capacitor mounting and via fanout.