Issue link: https://iconnect007.uberflip.com/i/1153097
82 DESIGN007 MAGAZINE I AUGUST 2019 path. The vertical reference plane change rule identifies instances of signals transitioning from one layer to another as well as the place- ment of stitching capacitors or stitching vias near those nets. Timing on high-speed nets is incredibly im- portant for proper functionality, especially on DDR nets. If DDR signals do not reach their destination within proper timing constraints, the memory may not work properly. Timing is- sues occur for a multitude of reasons, includ- ing transmission line propagation delay due to layer stackup, dielectric properties, and trace routing. Because delay issues are often caused by the unique physical properties of a PCB, the delay and length matching rule can automati- cally calculate necessary values from the de- sign's layer stackup, and then check for equiv- alent delays and/or lengths on each net in a specified group. In DDR designs that use fly-by topology, stub length is important for proper function- ality. The fly-by topology rule checks to make sure that nets with fly-by topology are designed within the proper constraints. The crosstalk coupling rule will help identi - fy areas on a design where unwanted crosstalk occurs on sensitive nets. Crosstalk can cause serious timing and functionality errors, and can also be very difficult to manually diagnose on a manufactured PCB. The power/ground width rule checks for nar - row trace widths on power and ground nets. If power and ground traces are not designed to be wide enough, the resulting current on that net can be insufficient. This may lead to a host of problems including, but not limited to, a lack of adequate power supplied to components as well as unnecessary heat production. The signal supply rule checks for discontinu - ities between an integrated component's sup- ply planes and its connected traces' reference plane. These types of violations can lead to po- tentially strong radiation, and as a result, EMI failures. The filter placement rule checks for the pres- ence of filters within a close enough proxim- ity to a connector's pins. To protect sensitive signals, as well as prevent radiation, filters are used to suppress noise that may be present on a connector. The absence, or misplacement, of filters on connectors can lead to serious EMI is - sues and failures. The return path rule ensures that the tested signals have a sufficiently low-impedance re- turn path. With the increase in today's high- speed circuit design requirements, as well as the decrease in PCB size, adhering to proper return path rules is incredibly important. If the return current on a trace is not able to properly flow underneath the conductor, it can instead take an unintended path through other areas of your circuit, possibly resulting in EMI issues. DRC for First-pass Success With tightly linked PCB layout and DRC tools, designers can ensure that their PCBs will not fail as a result of unnoticed SI, PI, EMI, and safety violations. Editable parameters within DRC allow users full control to adapt each test for their specific design requirements. With the aforementioned rules, in addition to many more, DRC can reassure designers that their PCBs will function properly while reducing costly board failures and design respins. When designs meet all advanced electrical rule ex- pectations on the front end, companies can speed up their product's time to market, and ultimately improve profitability. DESIGN007 Rebecca Lord is a technical marketing engineer at Mentor, a Siemens business, who specializes in HyperLynx SI/PI. John McMillan is a member of the PADS Technical Marketing team at Mentor, a Siemens business.