Issue link: https://iconnect007.uberflip.com/i/1174596
OCTOBER 2019 I DESIGN007 MAGAZINE 75 reasons could be fine-pitch BGA(s), RF, high- voltage, high-current, sensitive analog or digi- tal signals, flex regions, etc. To automate rout- ing in and out of these areas, your layout tool should support area rules. Of course, routing for special areas like those mentioned can be done by hand, but this leads to longer design times and possible quality issues. To simplify the complexity that can be per- ceived with area rules, net class- es, and clearance groups, we de- fine it so that the entire design is automatically available for each area rule we create. Once one or several area rule schemes have been defined, we can adjust trace widths by layer, via usage, clearances, and the class to class matrix against clearance groups for each area scheme. Lastly, how do we deal with differential pair definition and pin pair assignments? Again, au- tomation will save a tremendous amount of time. Those designing the schematic should have the same capability to create rules as the PCB designer. From the rule entry environment, being able to find large groups of nets (or all nets) and combine them automatically as differential pairs reduces a lot of tedious, repetitive work. As shown in Fig- ure 3, when naming nets properly in the de- sign, we can use a prefix or suffix to find nets that need to be combined as differential pairs. Here's an example of how to name nets: XYZ- Figure 2: Class-to-class matrix. Figure 3: Auto differential pair generation.