Issue link: https://iconnect007.uberflip.com/i/1181966
NOVEMBER 2019 I SMT007 MAGAZINE 91 The solder paste distributions for the seg- mented stencil, Stencil B, were verified, and the values meet the targets. Only one graph, Figure 13, was included here because, in the case of Stencil B, the solder paste was inten- tionally printed over the vias. Details of the solder paste coverage are included for each ref- erence designator in Table 1. AXI Data Automated X-ray inspection (AXI) was done for each board, images were saved for each component, and an automated void% value was provided. Because the via diameter and the total solderable area are variable, the reported void% was adjusted to reflect each case. Raw void% data did not consider the actual solder- able area of the thermal pad, and it removed the plugged via area from under the void. The formula used to correct the raw void% num- bers is Equation 2: • A thermal pad is the total area of the thermal pad, which is 8.3 mm x 8.3 mm, in this case • A via is the area of via opening, or the solder mask around the via opening, as applies • Void% is the as-reported value • Void% corrected is the void value after the total solderable area is considered • N empty vias is the number of vias with no solder plugs intersecting a void Upon correction, some as reported void% values changed to either increase or decrease the void%, depending on the solderable area; number of vias in the thermal pad; and the number of vias plugged with solder due to printing and reflow. An analysis of the main effects interactions shows the average void% dependencies, as described in Figure 14. In terms of significance, all the factors con- sidered for the main effects interactions are calculated to be significant, including some of the second-order interactions. As expected, the average void% decreases with increased via pitch, for a lower number of vias, and with increasing via size. It is less intuitive to see that the average void size increased when solder mask doughnut is present around vias. For this reason, a tally by board and void% range was compiled in Table 5, which shows that PCA#13, 14, and 15 have the optimized outcomes in terms of void- ing: all void on these 110-mil boards assembled with dot solder paste deposits is below 50%. For each of these three boards, only two ref- erence designators show values between 25% and 40% void. These reference designators do not have sol- der mask doughnut around vias. Figures 15, 16, and 17 show these reference designators, and the other three identical locations on each board. Figure 13: Thermal pad solder paste area—Stencil B. Figure 14: Main effects of solder mask (sm), via array, via size, via pitch, stencil type (dot=0, segmented=1), board thickness, and solder paste coverage on the corrected void% means.