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70 DESIGN007 MAGAZINE I NOVEMBER 2019 1. Organic The high Tg, low CTE organic base material outlined in Part 1 is commonly furnished with a seed layer of thin copper foil bonded onto both surfaces. Following laser ablation of the via holes, the surface is coated with a photo- resist, and the circuit pattern is imaged, devel- oped, and made ready for a semi-additive plat- ing process to fill via holes and form the con- ductor pattern. The copper seed layer that re- mained on the substrate's surface after pattern plating is chemically etched away, leaving only the conductor pattern. Additional copper cir- cuit layers can then be built up onto the base to further increase circuit density, utilizing the more conventional and well-established PCB fabrication processes. 2. Silicon Silicon-based interposer fabrication requires a rather specialized and complex sequence of processes that begin with via-hole formation. Although laser ablation can be adopted for forming the microvia holes, the process most commonly employed for volume applications uses a deep reactive-ion etching (DRIE) pro- cess, often referred to as the Bosch process. This methodology can provide very small hole diameters that range from 5–20-microns. In preparation for conductor forming and via fill- ing, a seed layer of copper or tungsten is ap- plied to enable electroplating the additional copper required to complete the via-fill opera- tion. Further pattern imaging and plating pro- cesses are engaged to provide interconnect fea- tures on the outer surfaces of the silicon sub- strate. 3. Glass Glass may be furnished in a wafer format but is more commonly furnished as panels as large as 500 mm square. Although the initial fabrication panels are rather large, users may specify segmenting the large panel in order to furnish a size that is more suitable for their ex- isting assembly systems. In regard to substrate fabrication capability, microvia hole diameters can range between 10–30 microns with a pitch in the range of 50–100 microns (depending on the hole diameter). For the initial hole-forming process, the fabricator may employ one or a combination of ablation technologies: laser ablation (CO 2 , excimer, UV), electrostatic discharge, me- chanical drilling, chemical etching, and/or micro sandblasting. In regard to conductor forming, several methods are available for metalizing glass, including copper alloy plat - ing similar to that described for the silicon- based substrate, deposited silver paste, and precision printing using silver and copper impregnated inks. Design Guidelines The design guidelines furnished in Table 1 relate to copper alloy via filling and conduc- tor formation. The geometries furnished were developed from research I did and consensus among several colleagues involved in the tech- nology. The data shown may not reflect the ca- pability of all suppliers in their respective cat- egories, but supplier companies will general- ly furnish the designer with alternative design guidance related to their material sets and spe- cific process capabilities. The supplier-devel- oped interposer design guidelines will general- ly reflect factors derived from their experience, ensuring that they will likely furnish a reliable product with a high degree of quality and pro- cess yield. As detailed earlier, the platform for mount- ing the die is typically one of three material sets: high Tg glass-reinforced epoxy laminate, super stable silicon wafers, and high impact glass panels. Because of the relatively high I/O required to interface multiple die, these inter- posers commonly adopt a uniform array-con- figured ball or bump contact design for the next level interface. Limiting the semiconductor package size continues to be a factor as well; however, the overall package outline will always be con- trolled by the size of the largest die and number of interface contacts. The base structure (in- terposer) selected must furnish a surface area large enough accommodate the I/O interface and mechanically stable enough to withstand