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60 DESIGN007 MAGAZINE I JANUARY 2020 To better meet their performance and min- iaturization goals, manufacturers are looking for higher functionality for their semiconduc- tor packages. For that reason, many manufac- turers will rely heavily on more innovative IC package solutions, often integrating a number of already proven functional elements within a single-package outline. This capability has been stimulated by the rapid deployment of new semiconductor packaging methodologies from a broad number of both domestic and offshore companies that understand that new product time-to-market can be the difference between leading and following. The key enablers for providing intercon- nect for these new generations of multifunc- tion semiconductor elements is choosing the best package substrate or interposer struc- ture for the specific application. PCB design- ers will realize that the base material and in- terconnect metalization processes utilized for the traditional multilayer glass-epoxy compo- nent mounting base materials are very differ- ent from base materials common to semicon- ductor fabrication. Furthermore, the design rules for via formation and circuit geometry will have a significant difference. On the other hand, these high-density semiconductor pack- age platforms are essentially miniature printed circuits requiring the same tools and skills de- veloped for PCB design. The following describes examples of both mature and evolving single-die package varia- tions: • Single-die ball grid array (BGA) and fine-pitch BGA (FBGA) packaging • Die size and flip-chip package technologies • Fan-in wafer-level packaging (FIWLP) • Fan-out wafer-level packaging (FOWLP) Single-die BGA and the FBGA package fami- lies commonly rely on either traditional face- up wire-bond or facedown flip-chip process- ing for interconnecting to a package substrate. The substrate is designed to redistribute the die terminals on the top surface of the pack- age substrate to a PCB-compatible array con- tact pattern on the bottom surface. The die el- ements mounted onto the top surface will be coated or molded over with a polymer com- position, and for board-level assembly, alloy spheres or bumps are furnished on the bot- tom surface. Die-size BGA (DSBGA) generally adopts the die facedown approach. The interface between die and interposer may utilize flip-chip pro- cessing, but wire-bond and lead-bond process- ing are more common. A good example of the die-size package using a wire-bond interface is the center-bond memory family of products il- lustrated in Figure 1. PCB Design and HD Semiconductor Packaging Designers Notebook by Vern Solberg, CONSULTANT Figure 1: Center wire-bond die-to-substrate interface.

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