Issue link: https://iconnect007.uberflip.com/i/1199133
JANUARY 2020 I DESIGN007 MAGAZINE 63 choosing a package solution that can achieve the performance objectives and cost con- straints. 3D die-stacking technologies have evolved as a practical, low-risk solution for a number of homogeneous memory and heterogeneous, system-in-package applications. The vertical integration of proven, high-yielding die ele- ments onto a single substrate will enable short- er development cycles and minimize overall development cost. In regard to reaching prod- uct objectives, the short interconnect between stacked-die elements will improve functional performance and minimize power, which is a key issue for portable and handheld products (Figure 3). 3D package-stacking offers practical solu- tions for pure memory applications as well as mixed-signal and logic and memory applica- tions. Typical applications include the integra- tion of high-density flash, DRAM memory, dig- ital baseband, and processors within a single package outline. Vertically mounting one or more pre-packaged die elements (package-on- package) is preferred by many over die-stack packaging because each level in the stacked package configuration can be pretested before joining (Figure 4). 2.5D represents a viable approach for inte- grating very high I/O, fine-pitch semiconduc- tors for both single- and multiple-die package applications. A primary challenge to the PCB design professional is dealing with the exces- sive increase in the package I/O and the shrink- ing space between terminals. Current examples include a semiconductor die with a terminal pitch range of 40–60 μm (~0.0016–0.0024") and a terminal geometry as small as 20–30 μm (~0.0008–0.0012"). Al- though the individual die elements may be fur- nished with a uniform array terminal format, the terminal size and pitch are often far too small for conventional PCB fabrication capa- bility. Users have realized that mounting one or more uncased die elements onto a silicon, glass, or TCE-matching organic-based inter- poser enables higher-density circuit routing and significantly shorter interconnect for criti- cal signal paths. And with a majority of the in-package interconnect accomplished on the interposer's surface, the interface between the component(s) and package substrate can be significantly less complex (Figure 5). This, in turn, allows the contact pitch on the package substrate to increase, simplifying the design Figure 3: Stacked die packaging. Figure 4: 3D package stacking.