Issue link: https://iconnect007.uberflip.com/i/1202019
36 PCB007 MAGAZINE I JANUARY 2020 cal design of equipment and for augmenting our tooling capacity for non-ITAR work. At the same time, we're adding in the U.S. a little more slowly. We're ramping up in Poland a lot faster than the U.S. because it's easier to find people in Poland than it is in the U.S. We're not a manufacturing economy anymore. Thus, you have to train people, even when they come out of school. They need a lot of train- ing to make circuit boards the way we want, whereas Poland has a manufacturing economy. Schools are more integrated with industry, so we've been fortunate to find good people very quickly over there. We are adding at both loca- tions, but it's easier to grow Poland faster. Matties: Last time, we chatted about typical cycle time for producing an HDI. Stepinski: It's one to two days per sequential lamentation. Matties: Versus a traditional HDI fabricator. Stepinski: We look at it in a few different ways. That's the theoretical time. If you have weird requirements or materials that aren't on the shelf, then everything changes. Typically, that's what we've been achieving. We have some pauses, as we're in startup mode because we have to analyze everything to finalize our reci- pes, but this is going to be our standard begin- ning in Q1. Matties: We see embedded technology more and more. Are you incorporating that into yours? Stepinski: We're doing passives right now. Matties: Are actives coming? Stepinski: For the actives, we understand the process of integration, but it's not the top item on our list. We have one customer who was interested in this and had the potential for some government funding of this project, but it hasn't been moving that quickly. Most of the customers have been focusing on realizing the benefits from our plating and wet processes. Some customers like the signal integrity as- pects, while others look at the stacked micro- via reliability aspect. We're getting extremely reliable stacked microvias with our process. Signal integrity was a big issue in the U.S. market because we have a SAP process. This allows us to hold much tighter tolerances than people doing pattern plating or people doing subtractive etching, etc. And this has been very interesting to a lot of people. The registra- tion is a single-digit, micron-scale registration. We have 10-micron tolerances layer-to-layer, so it's a different level. Everybody's looking at it in a different way. We have 20 differentiating competitive advantages, and not all of them hit with everybody, but a few do. Matties: What are your achievements right now with the plating process? Stepinski: We've demonstrated up to 40:1. We're planning up to 60:1 aspect ratios, and we have 6:1 through-hole fill that we've dem- onstrated already. Matties: These are record-setting numbers! Stepinski: Yes, for the industry, and we're in the process of continuing to develop this capa- bility and make it more repeatable. We recent- ly acquired all of the key copper plating folks from the old i3 IBM company. They joined us, so we added close to 100 years of experience to our team in the past two months. It has been fantastic, as they've helped us develop recipes, and we're continuing to invest in this area to differentiate ourselves more. Also, AWP in 2020 will be making vertical equipment based on all the innovations in ver- tical that we came up with already. Specifi- cally, our first project is for internal use as a surface finish process, where there's a lot of interest in VeCS technology and RF cavities. It's challenging to get the surface finish down there to be clean. We're setting up a process that will do blind structures with a wide variety of surface fin- ishes—including ENIG, ENEPIG, autocatalyt-