Issue link: https://iconnect007.uberflip.com/i/1207026
66 SMT007 MAGAZINE I FEBRUARY 2020 heat is not dissipated adequately, the higher junction temperature (temperature of silicon) will slow the electrons down. In a way, the packages make it possible to speed things up. This is not all the good things that the pack- ages do. They also make it possible to inter- connect the signals of all the silicon on the board so that the electrons can all talk to each other. Last, but not least, they provide a safe shelter to the silicon. Being homeless is no fun for the silicon, especially if the environ- ment around it is full of humidity and heat. A balanced way to think about a package may be that even though they slow the electrons down because of the capacitance and induc- tance of their leads and wire bonds, the pack- ages also provide useful functions, such as powering, interconnecting, and shelter for the safety and comfort of its inhabitant—the silicon inside. Despite the good things the packages do, many designers are trying to get rid of them anyway because they don't like any degrada- tion in silicon's performance. One can get rid of the package by using bare silicon. Bare sili- con is generally used as chip-on-board (COB) or flip-chip. There are some real differences in these terms. The COB term is used when the silicon is either wire bonded to the board directly or is used in the form of tape-auto- mated bonding (TAB). However, chip and wire and TAB add wire-bond inductance. The high- est performance is achieved when the bare sil- icon is directly flipped over and bonded to the underlying substrate. No wire bonds or leads are involved in the flip-chip process. One can achieve higher performance with bare chips when using them as chip and wire or flip-chip, but you create one major new prob- lem. We should note that in addition to the package functions mentioned earlier, the pack- ages also allow the pretesting of silicon before being soldered to the board. Out of all the mul- tiple chips on the board, it takes only one bad silicon to render the entire assembly worthless. To correct the problem, you have to remove and replace the bad silicon, but reworking bare silicon on a substrate is not a piece of cake. On the other hand, if the silicon is housed in a package, the test sockets, and the whole burn- in and test infrastructure, are in place to enable the use of only functional silicon. This issue of not being able to test bare silicon is referred to as a "known good die" (KGD) problem. It is not easy to test a bare die, although the industry has made good progress in this area. If that silicon is housed in a pack- age (or used as a TAB device), the problem of using bad silicon does not arise. If you insist on using the bare silicon to achieve the per- formance you need, you can use flip-chip but must be willing to pay a higher cost in terms of more rejects due to a KGD problem. It is possible to achieve better performance if one is willing to pay a higher cost. There are cer- tainly applications where it is worthwhile to pay a higher cost to achieve the needed perfor- mance, but it is generally in niche applications, such as multichip modules (MCM). The solution for the industry may not be necessary for getting rid of the package but developing more efficient packages that can perform the traditional function of the pack- age of protecting, powering, interconnecting, and providing a KGD without a significant pen- alty in performance. However, if you look at the R&D budget and effort on package versus silicon, there is no comparison. All the dollars are going into silicon development. We need that progress in silicon technology, but you cannot achieve the highest performance with a poor package. While we may not be able to get rid of package parasitics entirely, we are on Despite the good things the packages do, many designers are trying to get rid of them anyway because they don't like any degradation in silicon's performance.