Issue link: https://iconnect007.uberflip.com/i/1219242
MARCH 2020 I DESIGN007 MAGAZINE 39 Figure 3 illustrates the ringing (red) in an unmatched transmission line. This ringing, which is also represented by over/undershoot (right), is dramatically reduced by terminating the transmission line with an 18.7-ohm series resistor (blue). 2. End Termination Multi-drop bus topologies require paral- lel or end termination, which prevents re- flections from being formed at the transmis- sion line ends. With DDR3/4 memory de- vices, for instance, the fly-by address, con- trol and command (ACC) signals should be routed as close as possible to the memory de- vice pins and the parallel termination placed at the end of the line (Figure 4). The resistor values are twice that of the transmission line as they are in parallel from an AC perspec- tive. Short stubs can be used to connect the passing signal to each memory device in se- quence, but the longer the stubs, the higher the capacitance. This stub capacitance, along with the parasitic input capacitance of the re- ceiver pin, creates an imperfection in the ter- mination network. Figure 4 illustrates a typical DDR3 fly-by to- pology with the termination at the very end of the final load. Also, the passing address signal trace goes directly to the receiver pins with no stub. This is the ideal scenario. In this case, there are no reflections from the termination, which can be seen from the waveforms. pulse adds to the initial pulse to form a full voltage wave, so we get the signal we want at the load. The reflected pulse travels back to the source. When it reaches the series terminator, it sees the series resistor (24 Ω) plus the source im- pedance (26 Ω) totaling 50 Ω. Since the trans- mission line is also 50 Ω, there is no disconti- nuity of impedance; therefore, there will be no reflection. The signal will be totally absorbed by the terminating resistor and the source im- pedance, preventing further ringing. A receiver located at the very end of the trace will see an almost perfect signal edge. But a re- ceiver in the middle or near the resistor will first see a 50% signal and then a 100% signal. Because of this, series termination is only used when there is only one receiver/load, and that receiver must be located at the very end of the transmission line. To determine the value of the series termi- nator, the source impedance must be extracted from the IBIS model of the driver IC. Subtract- ing the source impedance from the trace char- acteristic impedance gives the required series terminator value (Figure 2). In the previous example, using a 12 mA LVC- MOS 1.8V driver of a Spartan 6 FPGA, an 18.7- ohm series resistor is required to match the driver to the 51.67-ohm trace on the outer lay- er. This is automatically derived from the IV curves of the Spartan 6 IBIS model by the iCD Termination Planner. Figure 3a and 3b: Ringing is reduced dramatically by adding a series terminator (simulated in HyperLynx). a b