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48 DESIGN007 MAGAZINE I MAY 2020 Semiconductor package specialists contin- ually work to improve high-volume manu- facturing process efficiencies while reducing manufacturing costs. A majority of the com- mercial semiconductors are built-up on the surface of a circular-shaped silicon wafer with metalized terminal features at their perimeter to accommodate wire-bond interface with a lead-frame or package substrate. To enable di- rect, face-down mounting to a package sub- strate or host PCB, the aluminum wire-bond sites on these products must first be processed to provide an alloy (typically copper) that will accept traditional solder ball or bump termina- tion features. When die have a perimeter terminal spac- ing that is considered too close for efficient circuit routing, it is common practice to em- ploy an additive metalization process on the active surface of the die to provide a conduc- tive interface from the wire-bond lands at the die elements perimeter to a wider-spaced and more uniform array configured terminal pat- tern. Commonly referred to as fan-in, wafer- level package (WLP), the process for adding a metalized redistribution layer (RDL) connect- ing the original wire-bond lands to an array- configured terminal feature is accomplished while the die elements remain in the original silicon-based wafer format (Figure 1). While the majority of the semiconductors se- lected for face-down interconnect can utilize the RDL processes noted, an expanding num- ber of small-outline, very-high I/O, silicon- Panel-level Semiconductor Package Design Challenges based processors are really not suited for con- ventional fan-in RDL processing. Fan-out, Wafer-level Packaging (FOWLP) The most practical solution for mounting and interconnecting very-high I/O, small-out- line die to a substrate or PCB is to expand the terminal pattern outward. The process com- monly utilizes a prepared silicon wafer base with metalized RDL designed to mount and in- terconnect the higher density die element to an array-configured terminal feature is outside the perimeter of the die. Metalization provided on the silicon wafer base redistributes the termi- nal features on each die to a pattern of plated micro-via holes that interfaces with metalized Designers Notebook by Vern Solberg, CONSULTANT Figure 1: Fan-in with RDL WLP.

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