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MAY 2020 I DESIGN007 MAGAZINE 53 circuit package technologies can be qualified using procedures and test conditions based on experience with similar technology previously qualified." For example, semiconductor package devel- opers are currently applying established JEDEC standards that basically require the end-prod- uct to be subjected to three solder reflow cy- cles at 260°C for preconditioning followed by 1,000 cycles through temperatures that range between –40°C and +125°C, as well as a high- ly accelerated temperature and humidity stress test (HAST) lasting 96 hours at 121°C with 85% relative humidity. Some experts, however, are concerned that current test standards may not identify reliability risks for all commercial-use environments. The iNEMI study noted, "While previous experience is important to consider, it cannot be the only criterion and relying too much on past experience may result in over- looking new failure modes and/or new wear- out mechanisms." In regard to package manufacturing pro- cess refinement, reaching satisfactory levels of throughput while maintaining quality objec- tives are not trivial issues. Developers have had to overcome a number of obstacles for each process variation. Matters that needed to be re- solved include the selection of the most suit- able carrier panel material, achieving precise die placement capability, dealing with mold material shrinkage and die shifting during the mold curing process, overcoming panel warp- ing during the metalization process, and de- fining the most robust die thickness and mold cap thickness ratio. DESIGN007 References 1. Dr. Tanja Braun, "Status FOPLP," Fraunhofer IZM, Germany. 2. C. Grosskopf, F. Xue, D. Locker, S. Thomas, J. Zheng, & M. Tsuriya, "Benchmarking of Qualification Methodolo- gies for New Package Technologies and Materials," 2019 International Conference on Electronics Packaging (ICEP), Niigata, Japan, 2019, pp. 1–6. Vern Solberg is an independent technical consultant, specializing in SMT and microelectronics design and manufacturing technology. To read past columns or contact Solberg, click here. The goal of the GARD program is to establish theo- retical ML system foundations that will not only iden- tify system vulnerabilities and characterize properties to enhance system robustness, but also promote the creation of effective defenses. Through these program elements, GARD aims to create deception-resistant ML technologies with stringent criteria for evaluating their effectiveness. In the first phase of GARD, Intel and Georgia Tech are enhancing object detection technologies through spa- tial, temporal and semantic coherence for both still images and videos. Intel is committed to driving AI and ML inno- vation and believes that working with skilled security researchers across the globe is a crucial part of addressing po- tential security vulnerabilities for the broader industry and our customers. (Source: Intel) Intel and the Georgia Institute of Technology (Georgia Tech) announced today that they have been selected to lead a Guaranteeing Artificial Intelligence (AI) Robustness against Deception (GARD) program team for the Defense Advanced Research Projects Agency (DARPA). Intel is the prime contractor in this four-year, multimillion-dollar joint effort to improve cybersecurity defenses against decep- tion attacks on machine learning (ML) models. "Intel and Georgia Tech are working together to advance the ecosystem's collective understanding of and ability to mitigate against AI and ML vulnerabili- ties. Through innovative research in co- herence techniques, we are collaborating on an approach to enhance object detec- tion and to improve the ability for AI and ML to respond to adversarial attacks," said Jason Martin, principal engineer at Intel Labs and principal investigator for the DARPA GARD program from Intel. Intel Joins Georgia Tech in DARPA Program to Mitigate Machine Learning Attacks

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