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MAY 2020 I DESIGN007 MAGAZINE 51 ing specialists currently utilizing systems con- figured to handle the 300 mm silicon wafer for- mat. In a presentation by Fraunhofer IZM [1] at a recent International Electronics Commission (IEC) standards meeting in Japan, the speak- er noted several key drivers supporting FOPLP technology: 1. Reduced overall package form factor 2. A thinner package profile 3. Improved electrical performance 4. Enhanced thermal management 5. The potential for greater component integration and design flexibility The packaging process variations described in the Fraunhofer presentation primarily fo- cused on a mold-first procedure where the sin- gulated die elements are placed, with the ac- tive surface face-up or face-down, onto the car- rier panel that is pre-coated with an adhesive. Mold-first FOPLP Following die placement, the populated carrier panel is overmolded with a reinforced polymer compound, fully encasing all die elements. The material selected for the carrier panel must closely match the CTE of the sili- con-based die elements (2.3 ppm/K) to min- imize the occurrence of die shift during the mold cure process, • Face-down FOPLP: After mold cure, the encased die elements are separated from the carrier panel exposing the active surface of the die elements. Surface metalization follows with pattern plating from the die terminal sites to a fan-out terminal pattern (Figure 3a). • Face-up FOPLP: The overmolded die ele- ments mounted in the face-up orientation (Figure 3b) is somewhat more complex be- cause it requires the removal of the poly- mer mold material to expose the termi- nal features for surface metalization and circuit pattern plating typical of that de- scribed above. The final process sequence for both process variations includes terminal formation (typi- cally a solder-compatible alloy ball or bump), marking, saw or laser singulation, and pack- age-level electrical test. Figure 3a: Face-down, mold-first FOPLP assembly sequence. 3b: Face-up, mold-first FOPLP assembly sequence.