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JUNE 2020 I DESIGN007 MAGAZINE 57 just five or so plane pairs, then most complex designs can't possibly be routed without cross- ing a split. This issue arises in nearly every in- tricate design. Adding 100 nF ceramic capaci- tors to span the split consumes real estate and creates a larger loop area, which, in turn, cre- ates emissions to some extent. The secret here is to design the stackup in such a way as to make use of planar capaci- tance, instead of bypass capacitors, by making sure each VDD/VCC region is closely coupled to a continuous ground plane. A plane pair is ba- sically a large capacitor that becomes more ef- ficient as the dielectric becomes thinner. Signal layers must also have an adjacent solid ground return plane to properly steer the electromagnet- ic wave. By using a combination of three plane layers as in Figure 4, the planar capacitance will provide an alternative return path to transverse the gap. This does not increase the plane count because the next signal layer in the stackup can also use the additional ground plane. Since the However, if the planes are at different DC po- tential, then a bypass capacitor can be con- nected across the planes at these points, as in Figure 3 (left). Unfortunately, this can pass AC noise between the power supplies. Two bypass capacitors, configured as in Figure 3 (right), is a much better solution, as this eliminates the transfer of power supply noise from one sup- ply to another. Although this does add an ad- ditional loop area, it also provides additional decoupling to the planes, reducing power dis- tribution network impedance. 3. Planar Capacitance The aforementioned solutions work for most designs, but are they the optimal solution for a high-speed signal to cross a split plane? A slot in the plane under two or more nearby sig- nal traces will usually cause return currents to overlap (shared return path), resulting in some degree of crosstalk. And since dense designs can have 20 or more power regions, spanning Figure 4: 3D view of the split plane stripline configuration. Figure 3: Eliminating the transfer of noise in the return path of split power planes (right).

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