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76 PCB007 MAGAZINE I JUNE 2020 that have lower Z-axis CTE stress, above the Tg of the material, so that they can form higher levels of stacked HDI. But there's still an end- point where you're going to probably have to stagger those vias. Many of the advanced SI requirements don't want to do that. That's one area where VeCS can be a real adjustment in HDI because that's not an influence in the reli- ability of a VeCS structure. The second thing that's moving it is that VeCS can utilize thicker dielectrics in layer-to-layer than HDI can. The capability of blind routing is over 10x HDI, and the plating depth is over 20 times the depth of HDI. If you had a 26-layer board that was six or seven lamination cycles of HDI, you can typically design it into a sin- gle lamination with VeCS and still have dielec- tric thicknesses between the layers of 0.1 mil- limeters or greater. That allows the high-speed signals to have much lower loss dB per inch from the signal itself. Those are two areas that the next-generation products are looking at, as chips are required to move closer and closer together, and technologies like PCIe try to put multi-chips on a single PCB. Those are some of the areas that we see that VeCS, with HDI or with through-hole, will enable copper intercon- nects on the PCB through the next generation, and maybe even the next generation. Johnson: What's the impact on the manufac- turing floor for technologies like VeCS? Dickson: In the beginning, the technology was designed to be built with conventional PCB manufacturing techniques, and that was NextGIn's goal. In the early stages, WUS uti- lized conventional technologies, convention- al routers, drill machines, and plugging lines to build the VeCS structures. But we've col- laborated with suppliers to build much more advanced equipment now than the original equipment we used, including high vacu- um encapsulation and via fill machines that helped us with the encapsulations to match or be better than laminate-type vacuum in- stallations and applications. We have very high-speed routing capabili- ties and CCD visual alignment now with our it. It's the same type of evolution that's hap- pening with 400G, which is already out there. We're building products to support it, initially using flyover optical cabling and even flyover copper cabling, because the interconnects and PCB technologies may not have been there to support that. But in the long run, they'll want to have that type of system built back into closer intercon- nects, and that's where the opportunities come in PCBs. Also, even moving to the next genera- tion of products may need those chips closer and closer and closer together, where flyover may not be the most desirable method of in- terconnect. Chip-to-chip locations will be there and most desired. I'm sure you see these types of requirements. Johnson: It's interesting how the dynamics are. You identified one of the technologies that is unique at WUS: VeCS. Dickson: Initially, we thought it would be cost- driven and that VeCS would be the pressure point because of cost. While that's still an av- enue of interest with almost everyone we talk to, the real pressure now is that it can innovate and do things that other interconnect technol- ogies are going to struggle with. For example, if you look at HDI technology, there are some significant issues with stacked HDI and reliabil- ity. Happy has made that very clear in some of the writings that he's done. We've worked on simulation tools to lower the amount of stress with stacked HDI and created HDI structures Moving to the next generation of products may need those chips closer and closer and closer together, where flyover may not be the most desirable method of interconnect.

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