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36 DESIGN007 MAGAZINE I AUGUST 2020 because the simulated V (load) output voltage directly gives us impedance without the need for further scaling. Figure 2 shows the result. The heavier line is the impedance magnitude with its scale on the left, the phase is the thin line with its scale on the right. We see four resonance peaks and one sharp dip on the plot. Peaks 1, 2, and 3 come from the antiresonances of neighboring capacitor banks. For instance, the first peak is formed by Lsrc and Cbulk, and the LC par- allel resonance of the 100-nH and 10000-μF values produce the 5-kHz resonance peak. To find the second peak, which comes from the series inductance of the Cbulk capacitor and the capacitance of Cceramic, we need to know the assumed inductance of Cbulk. You can notice that there are no series resis- tance and inductance symbols in series to the capacitors, so does it mean the simulation assumes zero values for those parasitics? In this regard, LTspice is unique among the SPICE circuit simulators. We can specify the usual simple parasitics without adding the corre- sponding schematic elements. The equivalent circuit, as defined in LT Wiki [5] , is shown in Figure 3. We can specify not only the equivalent series resistance and inductance but also two parallel loss elements and a body capacitance. These parameters will be frequency-independent entries. But how do we enter these parameters if we don't want to type up the SPICE deck manually? LTspice makes it easy, offering multiple options. Figure 4 on the left shows what hap- pens if we move the cursor over a capacitor in the schematic diagram and right-click. A window pops up where we can manually enter various attributes. On the right, you see the window which pops up when you hold the control key while you right-click. The two windows offer somewhat different choices. On the left—in addition to the equiva- lent series resistance, inductance, and body capacitance—we have only one parallel resis- tance entry. On the right, we can enter every parameter listed in Figure 3, including the ini- tial condition, temperature, and the multiplier (m or x), which is a convenient way to simplify the schematics if we have m number of iden- Figure 2: Impedance magnitude and phase of the simple PDN shown in Figure 1.

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