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AUGUST 2020 I DESIGN007 MAGAZINE 37 tical capacitors connected in parallel. We can also hide parameters or make them visible on the schematic using the checkmark in the last column. For the schematics shown, I turned on the feature only for the capacitance value; other- wise, the view would become very crowded. Notice that in Figure 4, I show the actual para- sitic values that were used to generate Figure 2. Figure 3: Screenshot explaining the capacitor equivalent circuit in LTspice. Figure 4: Options to enter parasitic values for capacitors in LTspice. Table 1: Parasitic values of capacitors that were used to generate Figure 2. Now, we see that the series inductance of the bulk capacitor is 10 nH, and this creates the anti-resonance with the 100-μF ceramic capaci- tor. From these two values, we get a 150-kHz antiresonance frequency, and that is exactly where Peak 2 is. Peak 3 is at 150 MHz, and it appears to be split by the sharp and deep Notch 4. Table 1 summarizes the capacitor- parasitic values for all four capacitors. We may wonder if the values in Table 1 rep- resent reality because ESR and ESL for the ceramic capacitor appear to be unrealistically low. Yes, it would be unrealistic to expect these values from a single capacitor, but if we imag- ine that these values represent ten pieces of 10-μF ceramic capacitor with 5-mOhm ESR and 1-nH ESL in each, then it looks reasonable. If we move on to look at the resonance at Peak 3, we realize that it is formed by the 10-nF Cdie capacitance and the equivalent induc- tance of the entire network looking back from the silicon, which is the well-known die-package

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