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102 DESIGN007 MAGAZINE I AUGUST 2020 The stiffener's edge on a thin FPC could cre- ate a stress area. To avoid cracks or tears in the close proximity to stiffener, a space between the stiffener edge to a via pad edge should be in a range of 1–1.8 mm, depending on the stiff- ener type. The minimum clearance between the two stiffeners has to be considered. For example, a distance of more than 0.6 mm should be provided between a stiffener located on the top side and the second stiffener located on the bottom side of the FPC. The static and dynamic bend areas of a flex- ible circuit are difficult to design. Traces must be routed perpendicular to the bend area (Figure 7). The designer can find minimum trace width and spacing in the fabricator's capability sec- tion. Minimum trace spacing also depends on the copper thickness on the inner layer. For the calculation of the external layer's minimum trace spacing, copper plating should be added to the copper thickness of the trace. High-speed designs always include con- trolled impedances. The reference planes for single-ended and differential pairs should be carefully considered. Copper is the main ingredient that adds rigidity to any construc- tion. Knowing that, an appropriate technique will be applied to each case. If the FPC has no bend requirement, a multilayer construc- tion is possible. The preferable FPC type for dynamic bend is one layer construction. How- ever, double-sided adhesiveless substrate and even three-layer with an air gap will also work for dynamic bend. For controlled impedance (microstrip), at least two signal layers are required, where one of the layers is a reference plane. When con- trolled impedance signals are routed on the area of a dynamic bend, the designer should consider air gaps in the stackup. For signal integrity improvement, blind and buried via techniques can be useful. This technique allows via stub elimination in high- speed applications. However, this production technique costs extra. Using a low-profile additive copper deposi- tion technique makes it possible to produce 100-Ohm differential with 1-mil trace width and 1-mil spacing. For high-speed designs, EMI is always a concern. Shielding techniques are applied. The perfect EMI shields are silver films. These films' thick- ness could vary from 22–32 μm. However, at frequencies higher than 10 GHz, the mate- rial must be tested since the efficiency of the films could be deteriorated (Figure 8). Tolerancing of FPCs is very important due to the nature of materials. In comparing thick adhesive and coverlay mate- rials and thin adhesiveless laminates, the designer should understand that the material movement will be different for each of these materials; as Figure 7: Trace routing in the bend area. Figure 8: Shield film application.