Issue link: https://iconnect007.uberflip.com/i/1284035
SEPTEMBER 2020 I SMT007 MAGAZINE 107 Table 6: DOE #4 IST test results (low). Conclusions from the DOE tests indicate that electroless copper deposits are responsible for the majority of weak microvia interface fail- ures and that the newly released IPC-6012E does not require extended testing or micro-sec- tions, creating a risk of positive results. Gerry Partida Gerry Partida, field application engineering manager at Summit Inter- connect, presented on "Current Concerns Over Microvia Failures." He reviewed concerns regard- ing the reliability testing of microvias, provided an overview of HDI pro- cesses, and presented the use of current test methods. In particular, he emphasized the superiority of testing with IPC-D-coupon and IPC-TM-650 test methods 2.6.7.2 and 2.6.27. Gerry also presented data that showed that tra- ditional thermal testing using IPC-2.6.7.2 will pass coupons that fail reflow. IPC-TM-650- 2.6.27B found 17% of the coupons that passed the thermal cycling test failed the SMT reflow test in the first few reflow cycles. Failure analysis indicated that the failures occurred near the center of the coupons. Test runs were repeated using lower blind via aspect ratios and larger laser drill diameters, and all coupons passed the reflow tests 100%. It is critical that tests be performed on micro- vias using production materials, design rules, stackups, and pre-/post-clean processes using the IPC-TM-650-2.6.27B test method before products are shipped to customers. Dr. Maarten Cauwe Maarten Cauwe, Ph.D., team leader of advanced packaging at IMEC-CMST, explained "Microvia Tech- nology Assessment for Space Applications." Dr. Cauwe is a member of the IPC Special Committee on the weak microvia interface problem and a fre- quent contributor to his work with the ESA at IPC APEX EXPO and SMTAI. The work presented is part of the ongoing ESA project on high-density PCB assemblies, led by IMEC and with the aid of ACB and Thales Alenia Space Belgium. The goal of the project is to design, evaluate, and qualify HDI PCBs that can provide a platform for assem- bly and the routing of small-pitch area array devices (AAD) for space projects. Two catego- ries of HDI technology are considered: two lev- els of staggered microvias (basic HDI) and up to three levels of stacked microvias (complex HDI). Within the project, various test methods for evaluation microvias are assessed. Intercon- nection stress testing (IST) and reflow sim- ulation combined with traditional thermal cycling is currently the method of choice in ESA's ECSS-Q-ST-70-60C standard for qualifica- tion and procurement of PCBs. Alternatives as