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SEPTEMBER 2020 I DESIGN007 MAGAZINE 37 current density. The parameters of the simula- tions are shown in Table 2. The trace width was varied from 0.6 mm to 5.0 mm, but the via dimensions remained constant for all simulations. The applied cur- rent was adjusted so that the via temperature also remained constant (to the degree practi- cal). The trace temperature for each simula- tion was recorded at a point mid-way between the beginning of the trace and the center of the via. Figure 3 illustrates the thermal pattern for the top layer of the simulation for the 2.0 mm trace carrying 5.25 A. The results of the simulations are shown in Table 3 and Figure 4. The first thing to note is that when the trace width is small, such that the via cross-sectional area is about the same as or larger than that of the trace, the via tem- perature is less than the trace temperature. This is because the via resembles an internal trace, completely surrounded by board dielec- tric, and so it cools more efficiently than the parent trace [7] . As currents (and therefore tem- peratures) increase, vias do get warmer than the parent trace, but only slightly so. a constant current density everywhere, but sig- nificantly different temperatures in the three segments. 4. Current Density and Vias One of my biggest concerns is when de- signers base decisions regarding the number of, or the size of, vias on the current den- sity flowing through them. Dr. Adam and I have already shown [4] that the temperature of a via is not related to the magnitude of the current flowing through it. It depends on the temperature of the parent trace. That is be- cause the trace acts as a huge heat sink for the via and conducts the heat away from the via. This is exactly analogous to how the heat sink above a computer microprocessor con- ducts the heat away from and protects that component. Dr. Adam and I used simulation to illustrate that point a few years ago. Knowing that that would be hard for many people to accept, we (with help from Prototron Circuits [5] ) later ex- perimentally verified those results. I recently ran another set of via simulations regarding Figure 3: Thermal profile of the 2.0-mm trace carrying 5.25 A. Via is at the center of the board. Table 1: Simulation model parameters. Table 2: Via simulation parameters.