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36 DESIGN007 MAGAZINE I OCTOBER 2020 Feature Interview by the I-Connect007 Editorial Team In Part 1 of this conversation from SMT007 Magazine, Rita Horner of Synopsys provided a general overview of the IEEE Heterogeneous Integration Roadmap (HIR)—a document that provides guidance for IC, PCB, and package designers, broken down by industry segment and performance requirements. In Part 2, Rita shares her perspective from the IC side, as well as how the HIR might affect what happens on the PCB design and manufacturing side in the next few years. Nolan Johnson: You're working at Synopsys on multi-chip integration in a package EDA product. Compare and contrast the difference between multi-chip products today and where the HIR will take us. How is it different? Rita Horner: As you mentioned, the HIR cov- ers many grounds, and it's not just one market or application space. It's hard to just general- ize that. I talked about technology limitations, but there is an economic aspect of it because it's not cheap to make these devices. Even a monolithic die in a package is expensive when it's complex and large in the advanced tech- nology nodes today, such as five nanometers or smaller. When you're not getting the yield, it's going to make it even more expensive. Very few people can afford to design in the advanced technology nodes. Heterogeneous integration in a package would enable an entry path to the high-end markets much more eas- ily. They don't have to design everything in the most expensive technology nodes to achieve high levels of integration. Johnson: Just because a small function of the design needs high density doesn't mean the entire design has to be that way. Horner: Five-nanometer technologies may not be optimal for the high performance I/Os that may be needed. With the thinner oxide layers in the smaller technology nodes, the thresh- old voltages are lower and more challenging to design high speed I/Os. These are the physical layers. High-speed SerDes may be more optimal in older technology nodes, whereas the rest of IEEE's Heterogeneous Integration Roadmap, Part 2

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