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Design007-Oct2020

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28 DESIGN007 MAGAZINE I OCTOBER 2020 ing the gigahertz range. You had to think of everything as transmission lines. Shaughnessy: When top PCB design instruc- tors like Rick Hartley, Lee Ritchey, and Eric Bogatin teach, they say every wire and every trace is a transmission line, and you have to put it that way, or you'll be out of luck. With the rise times and speeds, everything is so fast, and there is no leeway. Schutt-Ainé: But that's more at the PCB or package level. The chip is a different story because everything is so small. You don't worry too much about inductance or radiation or antenna type problems. The chip is going to be mounted on your package, and the chip is going to be running really fast. Shaughnessy: It seems like it's even more of this system-level awareness. Almost every- body involved in designing or building a cir- cuit board must have a system-level outlook, or they're not going to be able to make all the right decisions. Schutt-Ainé: And it's going to become harder. In the course I teach, I always give the stu- dent this perspective. Look at a cellphone, for instance. With a typical design, back in the day, the voltage was 12 volts, and then it went to five volts, then to 3.6, 1.8, and 1.2. Now, it's coming down to even lower than one volt. The reason you're lowering the DC supply voltage is that you want low power, long battery life, and low power dissipation. But it makes the job a lot harder for the designer because the voltage budget is now very small. You need to have everything done within one volt. Even with a 0.6-volt drop, just running from the power supply to the power rail is bad news. Johnson: Let's transition to talking about your presentation. Schutt-Ainé: Sure. This is a modified version of the webinar that I gave two months ago as a chapter overview. We've had some discus- sions about the motivations for co-design, and as we outline the application, the designers are the drivers. They have to decide what is needed in those tools to somewhat facilitate the process of co-design, such as data centers, IoT, automotive, etc., and especially things like SerDes and high-speed links. I highlighted those two because a lot of what I do in my research relates to these applications. The way our technical working group was structured is we wanted the chapter to address some of the questions listed. What is the state of the art in co-design? What will drive the creation of these tools? What will the challenges be? How much value will having co-design tools add to HIR? How will all of this happen in the next five to 10 years? Traditionally, co-design is how you manage the chip, package, and board together. The chip level is very different than the package or the board. At the chip level, you worry about transistors, and their operation is highly non- linear. MOSFETs are nonlinear devices, and with the tools used for verification like SPICE, it's important to notice that the scaling takes place with technology. Essentially, they follow Moore's law. By contrast, with the package into the board level where things don't fol- low Moore's law, the scaling happens with the electromagnetic wavelength. Going to the board level, it is very similar to what you get at the package level, but you get additional tools because the dimensions are higher, so the electromagnetic extraction tools become more important. Given the fact that you may be dealing with different types of chips from different vendors, you need to have a way of handling the nonlinearities. For instance, the IC's form has come into play. The goal is to combine all these domains and develop a successful flow. People talk about vertical or horizontal co-design, but the verti- cal one is when you go from one domain to the other. Co-design is when you make sure you are aware of many different constraints. You're going from chip to package to board, but you are also incorporating constraints related to security, test, and thermal. All of those also have to be integrated, which will make the process a lot more complicated.

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