Issue link: https://iconnect007.uberflip.com/i/1295812
40 DESIGN007 MAGAZINE I OCTOBER 2020 somebody with board experience to work on the interconnect inside the chip? Horner: It's not so much board experience. You need to involve the board designer, though. You should not think about PCB design as an afterthought because you want it designed effectively. You're talking about these pack- ages getting to 100- by 100-millimeter dimen- sions. This is almost a PCB by itself. There will be a lot of balls on that to connect, which may mean lots of layers of board and make the end- product very expensive. When you have all the information, you can create a more opti- mal environment by collaborating for further optimization of each design layer. Johnson: I'm imagining how this would work for multiple manufacturers of sensors for auton- omous vehicles, all relying on a chip from one or two manufacturers. If there is design-spe- cific collaborating with the PCB, that changes how chip manufacturers provide application notes and instructions to a customer. Do you see that happening? Horner: That is what's happening in the mar- ket. If you own all the pieces that go into a package, that's one thing. But then when you're talking about mixing and combin- ing things, you need some standards. You need some definitions to create chiplets. If I am a chiplet manufac- turer that has a niche capability and want to enable other people to use it in their multi- die, I have to have a standard interface. We need more stan- dards to define inter- faces that can be used at the same time. The Open Compute Proj- ect (OCP) has gone one further step doing some proof of concept, making sure that it's not just the definition of the die-to-die interconnect; it also has to work. OCP focuses on the high-end computing and ensures that the needs are all met, even going up to the protocol stack. One member is organizing regular meetings on cataloging and what information is needed for different chiplets for smooth integration. As this organization is driving the initiative, we are asking, "What level of detail does every chiplet need to provide to enable this catalog- ing and end-user integration? How much detail do you have to provide?" If I'm getting one part from one vendor and another part from a different vendor, when I'm doing my power analysis, I need some level of detail from every device to do my analysis just for the die-to-die. Forget about going to the package, board, or high level and just mak- ing the connection. Ensure that the connection is done correctly and has the right width and spacing for the most optimal performance of the connection. DESIGN007 Editor's Note: Stay tuned for Part 3 in October's PCB007 Magazine. Figure 2: Heterogeneous integration. (Source DARPA)