Issue link: https://iconnect007.uberflip.com/i/1307491
62 DESIGN007 MAGAZINE I NOVEMBER 2020 The parts are then taken to an imaging department where a photoresist is applied to the panels, and the panels are imaged. Then, the image is developed and taken to the elec- troplating department where the now-exposed traces and pads are plated—hence the reason holes are compensated larger before the plat- ing process. After plating, they end up at the size and within the tolerance described on the fabrication drawing. A multilayer is slightly different. The core material is pulled and coated in the dry-film department, and the parts are also imaged. If a standard multilayer with no blind or buried vias exists (I will get into them later in this col- umn), the process in the plating department is a develop, etch, and strip process. The image is a negative image, so where the light sees the panel, it hardens the resist, thus protecting the traces and plane layers. IPC Standards Why did I talk about how a fabricator processes a given hole? Let's talk about IPC standards. However, I will not talk about Class 1 since most products are Class 2, 3, or even 3A. In a Class 2 IPC-6012 part, both external and internal holes can have as much as 90-degree breakout and still be acceptable (Figure 1). But for Class 3 and Class 3A, the external must have a minimum of a 0.002" annular ring after drill and plate, and the internal layers must have at least 0.001" annular ring. That means if the part needs to meet a higher class based on its function and applica- tion, you need to design the board knowing the fabricator will over-drill the plated holes approximately 0.004–0.005" over the hole's size stated on the drill/fab drawing. A 0.008" hole with a 0.012" pad would not be accept- able, as the part will be over-drilled by 0.004– 0.005"; in the case of Class 3 and Class 3A, the part must also have an additional 0.002" annular ring. Add to this that a fabricator has both a true position tolerance and a machine tolerance (normally ±0.003"), so truthfully, given Class 3 IPC-6012, the pad size should take into consideration all of these variables. Is that even feasible? Let's say the Class 3 IPC-6012 via size is 0.008" expressed as ±0.003" tolerance. If that were true, you would need to drill the hole at approximately 0.0138", and the machine tolerance plus the true hole posi- tion tolerance of ±0.003" would mean a 0.016–0.018" addition to the nominal hole size (again expressed as ±0.003"). Thus, the pad size would need to be 0.026". That is not feasible in board design where real estate/ board area issues exist. This brings me to the reason I bring up the fabrication process for holes in the first place. If the holes are simply vias, for many years now, I have told our customers (in my previ- ous life as a board fabrication guy) to call them out as ±0.003" the entire hole size. This way, a 0.008" via could be drilled at 0.008", and no compensation or over-drill would be required. This now means a Class 3 IPC-6012 part could be as little as 0.016–0.018" for a pad size and even less if negotiated with the fabricator if they have good control of their machine and true position tolerance. Figure 1: IPC annular ring acceptance criteria.