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NOVEMBER 2020 I PCB007 MAGAZINE 47 potential overplating of the outer layers as a re- sult of a longer plating time in order to obtain a solid copper plating in small via holes with a high AR. Three Variations of Laser Vias With Different Combinations Figures 2 a, b, and c show some combina- tions. For all three combinations, laser vias on the top (layers 1–2) and bottom (layers 14–13) are copper filled as they are placed in the SMD component pad; thus, they are soldered. Fig- ure 2a is the least challenging in terms of cop- per plating and also the most reliable and low- est cost to produce. Laser vias on layers 2, 3, 12, and 13 are stag- gered and filled with resin after electroless copper, electrolytic copper plating, and etch- ing. The same goes for the buried hole layers 3–12, often filled with epoxy. In Figure 2b, all laser vias are filled with cop- per and stacked on top of each other. There is a cost for copper filling of the inner laser vias, and the reliability of stacked vias is lower than in Figure 2a where they are staggered. The big change in Figure 2c, compared to 2b, is that la- ser vias are stacked on the buried hole (layers 4–11). The buried hole is now also clad with copper to secure the connection to the laser via, which is placed directly on top. Of the three examples, Figure 2c has the highest cost and is also less reliable than Fig- ures 2a and 2b. The lower reliability in Figures 2b and 2c is based on a potential expansion of the material in stackup that may affect the con- nection between the vias that are directly con- nected to each other. In certain cases, electri- cal properties must be prioritized, and lack of Figure 1: Eight any layer stackup. Table 1: Eight any layer impedances.