Issue link: https://iconnect007.uberflip.com/i/1309864
NOVEMBER 2020 I PCB007 MAGAZINE 49 production. The main reason is that they con- tain design issues that have not been clarified with the PCB manufacturer before the design begins, or the design is not in accordance with IPC requirements. Typical conditions are: 1. There is too great a distance between the layers where laser vias are used. 2. The copper is too thick in relation to the conductor widths to be etched and the distance between them. 3. The designer has not calculated that inner layers can also be plated when laser vias and buried holes are used. 4. The AR is incorrect, which especially applies to smaller drilled holes. The recommended maximum AR is 8:1 on buried and through-drilled holes. Laser vias have a recommended maximum AR of 0.8:1. 5. There is a misunderstanding of the use of laser vias, often defined as through-holes with a 0.1-mm diameter. Resolving the Layout and Making It Producible In these cases, we open a dialogue with the designer and give them an introduction and rec- ommendation on how their design can be made producible. Vias plays an important role in a PCB as signal speeds increase. A PCB design- er must be able to handle this. In general, we can say that vias constitute a discontinuity in the transition from a conductor and will affect the signal in designs with high-signal speeds. Capacitance can increase rise time, which re- duces speed. Therefore, designers must ensure a good impedance transition. The larger the pad diameter, the lower the impedance due to the increased capacitance. By removing non- functional via pads on the inner layer, the ca- pacitance can be reduced. A dangling via stub acts as an open resona- tor. When using laser vias, we have no stub. On traditional drilled vias, a stub can be removed with back-drilling. Drilled Via Hole Reliability The reliability of drilled via holes is affected by several parameters: 1. A reduction in the length of the hole will make the hole more reliable, which can be done by reducing the total PCB thickness or reducing the length of a buried hole. 2. An increase in the diameter of the hole can also provide increased reliability, but this is typically a non-option due to lack of space. For example, 0.2–0.25 mm can pro- vide increased reliability. 3. The choice of material—especially the co- efficient of thermal expansion (CTEz) and and elastic modulus or stiffness (Ez)—also contributes to increased reliability, but Ez is not mentioned on all datasheets. Table 2: IPC-6012E Table 3-4 Surface and Hole Copper Plating Minimum Requirements for Buried Vias >2 Layers, Through-Holes, and Blind Vias. Table 3: IPC-6012E, Table 3-5 Surface and Hole Copper Plating Minimum Requirements for Laser Vias (Blind and Buried). Table 4: IPC-6012E, Table 3-6 Surface and Hole Copper Plating Minimum Requirements for Buried Cores (2 Layers). Table 5: IPC-6012E, Table 3-11 Cap Plating Requirements for Filled Holes.