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68 SMT007 MAGAZINE I DECEMBER 2020 the signal path, improving both signal integrity and power integrity. Critical nets may suffer from crosstalk due to the dense routing within the fanout. The routing of differential pairs in between the pins of a 1.0-mm pitch compo- nent requires fine line widths and spacing. Dif- ferential pair routing in between the buried vias for 0.8-mm pitch components is no lon- ger possible. The pairs need to be split within the fanout area, and the effect on signal integ- rity will depend on the length of the split. The change in width on single-ended nets, as well as a change in the spacing and/or trace widths of a differential pair, will cause an impedance discontinuity. Choosing the appropriate layer build-up and via types will thus improve both route-ability and signal integrity. An important consideration in the defini- tion of technology parameters for HDI PCBs is that component pitch, and the number of I/ Os cannot be addressed independently. A high pin count component (>1000 pins) with 1.0- mm pitch can require the use of microvias to reduce the total layer count or to improve the shielding of controlled impedance lines. On the other hand, the escape routing of a 0.5- mm pitch component with only two rows of solder balls can be performed without micro- vias and fine line widths and spacing. Increas- ing the layer count to be able to route one or more high pin count components will result in an increase in PCB thickness, which impacts the minimum via drill diameter through limi- tations on the via aspect ratio and thus again restricts routing possibilities. To define the HDI technology parameters, the specifications of area array devices (AADs) used in past, present, and future space projects need to be known. Looking into the complex components for space that are currently under development, the ceramic column grid array (CCGA) with a pitch of 1.0 mm will remain the package of choice for the coming years. This is, for example, the case for the new Xilinx FPGA (RT-ZU19EG: CCGA1752) [1] , the CNES VT65 telecom ASIC (CCGA1752) [2], and ESA's Next Generation Microprocessor (NGMP, CCGA625) [3]. Column grid arrays with smaller pitch (0.8 mm) have been demonstrated in R&D [4], although no commercial implementations have been found. Ceramic ball-grid arrays (CBGAs) with non-collapsing, high Pb solder balls are used in military and aerospace applications [5]. At 0.8-mm pitch and beyond (0.5 mm), ceramic (i.e., hermetic) packages become a reliability risk as the smaller solder balls can no longer support the coefficient of thermal expansion (CTE) difference between package and board. A recent NASA study, therefore, investigated the reliability of plastic ball-grid arrays (PBGAs) with up to 1704 pins at 1.0-mm pitch and 432 I/Os at 0.4-mm pitch [6]. Increasing the capability for dense routing, signal integrity at high speeds, and a high num- ber of I/Os undoubtedly has its impact on reli- ability. Reducing line width and spacing, via pad size, and drill diameters all influence the manufacturing yield and quality and thus pres- ent a reliability risk. New materials need to be introduced to corroborate the increasing capa- bility demands without diminishing the reli- ability standards. High-density interconnect PCBs have been used for over three decades and are currently applied in all markets. Numerous studies on HDI technology and its reliability have been published. The returning theme in almost all HDI technology studies is that the technology can be very reliable if manufactured properly. Process control and quality assurance are key to reliable HDI PCBs. HDI Technology Parameters At the start of the project, a stakeholder work- shop was organized at the ESA ESTEC facil- ity in the Netherlands to provide an update to the HDI PCB section of the PCB and Assembly Technologies Roadmap for Space Applications [7] and to derive the requirements for HDI PCBs in space projects. Workshop participants were prime satellite contractors, equipment manufacturers, space agencies, ESA-qualified PCB manufacturers, ESA technical officers, and independent CAF experts. In preparation for the workshop, a ques- tionnaire was compiled to determine the driv- ers and technology parameters for HDI PCBs for near-term space projects (2018–2020) and

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