Issue link: https://iconnect007.uberflip.com/i/1313710
70 SMT007 MAGAZINE I DECEMBER 2020 with two levels of copper-filled microvias. Two levels of microvias are considered suffi- cient to route the AADs with 0.8-mm and 1.0- mm pitch. To minimize the reliability risk, the microvias are staggered with respect to each other and to the buried via in the core. Fill- ing of core vias with prepreg from the HDI lay- ers is preferred, and two sheets of prepreg are applied. The complex HDI technology will use three levels of microvias. The microvia configuration of choice is the semi-stacked option consisting of two stacked microvias plus one staggered microvia. Stacking three levels of microvias is considered a reliability risk. An IST prescreen- ing is performed within the project to deter- mine if the semi-stacked microvia configura- tion can meet the required reliability. If this is not the case, the full staggered configuration will be used as a backup solution. Via plug- ging and capping will be used for the buried vias in the complex HDI technology. The effect on the reliability of removing the non-func- tional pads and back drilling of the buried vias will be investigated as part of the complex HDI technology evaluation. Polyimide remains the material of choice for HDI PCBs in space applications. To accommo- date the needs for RF and high-speed digital applications, Panasonic Megtron 6 is included in the complex HDI technology evaluation. Low in-plane CTE materials are not seen as a priority for HDI in future projects. The use of a single sheet of prepreg for the microvias will be evaluated. Solder mask is a requirement for the complex HDI technology. Other surface finishes (ENIG, ENIPIG, ENEPIG, and EPIG) are of interest, but the focus of the project is not to evaluate alter- native surface finishes. The complex HDI tech- nology will be evaluated with both ENIG and ENEPIG (one finish per base material). Project Plan Figure 1 shows the overall concept for the HDIPCB project. During the workshop, the rel- evant AADs for space applications were identi- fied. Based on the mechanical (pitch, number of pins) and functional (data rate, controlled impedance) requirements of these compo- nents, the technology parameters and associ- ated design rules were determined. The goal is to achieve qualification status for the basic HDI technology. The PCB qualification is fol- lowed by assembly verification for 1.0-mm pitch CCGA1752 and 0.8-mm pitch CBGA323 components. Before launching the evaluation of the com- plex HDI technology, an IST prescreening will be performed to decide on the use of stacked Figure 1: Overall concept for the HDIPCB project.