Issue link: https://iconnect007.uberflip.com/i/1313710
72 SMT007 MAGAZINE I DECEMBER 2020 or staggered microvias. The evaluation of the complex HDI technology may lead to formal qualification for all or a subset of the tech- nology features, depending on the occur- rence of nonconformances in the evaluation. The subsequent assembly verification for 0.8- mm and 0.5-mm pitch PBGA components will be approached in the same manner, with the focus on evaluating the performance and iden- tifying uncertainties. Next to the qualification and assembly veri- fication activities, an extensive HDI reliability assessment is performed. The study focuses on three aspects: thermal reliability, microvia testing, and CAF testing. The via fatigue and thermal stress evaluations will be correlated with the modeling of the bare PCB. For CAF testing, a dedicated test vehicle is designed to match the requirements of the HDI technology parameters. An extensive test campaign using thermal cycling, convection, and vapor phase reflow assembly simulation, and interconnec- tion stress testing (IST) will be undertaken. In this article, the test vehicles, test meth- ods, and test results for the HDI qualification in accordance with ECSS-Q-ST-70-60C [9] are described. The outcome of thermal cycling, IST, and CAF testing is discussed. Other activi- ties within this project will be published else- where over the course of the project. Test Vehicles The qualification test vehicle (QTV) consists of a full panel design, including the following features: • Test structures for HDI qualification test flow – Coupon A/B with through-vias and component holes – Coupons B1, B2, and B3 for the microvia level 1, microvia level 2, and the buried vias, respectively – Coupon E for intralayer insulation resistance and dielectric withstanding voltage – Coupon H for interlayer insulation resistance and dielectric withstanding voltage – Coupon P for peel strength on outer layers – TVX and SLX procurement IST coupons • Coupons for outgoing inspection as detailed in clauses 8.2.2 and 8.2.3 of ECSS-Q-ST-70-60 [9] • BGA coupon which mimics (part of) an actual HDI PCB design – Real and daisy-chain component fanout for 1.0-mm and 0.8-mm pitch component ° CCGA, 1.0-mm pitch, 1752 I/Os (Xilinx Virtex 5QV FPGA) ° CBGA, 0.8-mm pitch, 323 I/Os (Teledyne e2v EV12AQ600 ADC) – Routing to Axon Nano-D (1.27 mm) and Smiths connectors KVPX (1.35 mm) The BGA coupon (Figure 2) mimics (part of) an actual HDI PCB design and acts as a "PCB" for the qualification test flow. The real com- ponent fanout for 1.0-mm and 0.8-mm pitch components are based on the actual pinout diagrams for the Xilinx Virtex 5QV FPGA and the Teledyne e2v EV12AQ600 ADC, respec- tively. Controlled impedance differential pair routing was applied to all relevant output pins. As high-density connectors can impose restric- tions on routing and are thus also driving com- ponents for HDI, two candidates are included in the BGA coupon. The differential pair inter- connections of the Xilinx Virtex 5QV FPGA component fanout are routed to eight KVPX connectors. The fanout of the Teledyne e2v EV12AQ600 is combined with the Axon nano- D connector. Two levels of staggered microvias can be implemented in different ways. For the 1.0- mm pitch fanout, the component pad is placed directly above the buried via. The micro- via between layers 1 and 2 is placed partially inside the component pad. The capture pad of the microvia between layers 2 and 3 is tangent to the target pad of microvia 1-2. The target pad of microvia 2-3 is connected to the buried via using a short trace. The advantage of this microvia configuration is that microvia 1-2 is not located above the buried via, although the short trace between microvia 2-3 and the bur-