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82 SMT007 MAGAZINE I DECEMBER 2020 (75 µm vs. 50-µm spacing). The exact nature of these failures is not yet known at the time of writing of this article, and failure analysis is ongoing. A dedicated test vehicle was designed to match the requirements of the HDI technology parameters. The design of this HDI CAF TV dif- fers significantly from the more widely used IPC test coupons and derivations. The layer count is twice as high (20 layers versus 10 lay- ers typically), doubling the number of opportu- nities for CAF, affecting drill quality, and intro- ducing a higher risk for contamination with foreign material. The use of sequential lamina- tion (risk of embrittlement) and internal plated layers (thick copper) makes achieving a good drill quality more challenging and better repre- sents the actual board. The rationale behind this test vehicle and, by extension, the CAF test methodology can be debated. CAF testing can be performed at different levels: material evaluation, qual- ification of a given design and material at a selected manufacturer, or as a batch release for each procurement. While material screen- ing, at possibly elevated stress levels, is rele- vant for material development and compari- son, it is insufficient since it does not take into account the manufacturing. Some experts are of the opinion that CAF is batch related and should therefore be done as part of the release procedure during outgoing test. In the ECSS working group, CAF testing as part of a qualifi- cation test flow was deemed an adequate com- promise. The possible variations in manufac- turing can be considered covered by the use of qualified manufacturers having a PID (pro- cess identification document). The CAF risk of a given design needs to be reviewed case by case to ensure that the qualification testing covers (i.e., is representative of worst-case or highest technological capability) for the pro- cured PCB design. Conclusion During the workshop, the relevant AADs for space applications were identified. Based on the mechanical and functional requirements of these components, the technology parameters and associated design rules were determined. Two categories of HDI technology are consid- ered: two levels of staggered microvias (basic HDI) and (up to) three levels of stacked micro- vias (complex HDI). This article presents the main results of the qualification test flow for basic HDI technol- ogy. The through-vias and buried vias reached the required IST endurance of 400 cycles. The microvia configuration for the 0.8 m pitch fanout might be the cause of the early fail- ure in IST. Electrical monitoring during ther- mal cycling showed only a minimal increase in resistance for both temperature ranges. Micro- sectioning after cycling did not reveal any cracks initiating in the barrel of the buried via nor any anomalies in the microvias. For the CAF testing, no failures were observed between microvias at 0.5-mm pitch, buried vias at 1.0- mm pitch, or PTHs at 1.27-mm pitch. Some failures occurred between buried vias at 0.8- mm pitch. Most failures were detected in the via-to-plane test structures, especially for the PTHs. All other tests in the qualification test flow were passed successfully. The qualification of the basic HDI technol- ogy is only the first step in this extensive study on HDI technology for space applications. An extensive reliability assessment is under- way. Various test methods for microvias will be evaluated to arrive at a test flow that can assure an adequate confidence level for both procurement and qualification. Figure 6: CAF test results for microvias in a straight configuration with a pitch of 0.5 mm.