Issue link: https://iconnect007.uberflip.com/i/1315894
22 DESIGN007 MAGAZINE I DECEMBER 2020 PCB impedance control is a routine specifi- cation on many boards. As geometries shrink, fabricators making TDR impedance measure- ments will start to see the TDR trace rising over its length. Most of the reason for this is the DC resistance of the trace. (Note that TDR traces may rise for two primary reasons: There is DC resistance in the trace, or the impedance is actually rising because the trace is tapering.) This DC resistance effect on the trace should not be confused with the characteristic imped- ance of the trace itself, which is unchanging with length. Designers should ask their PCB fabricator to use a measurement technique that de-embeds (or removes) the DC resistance from the TDR measurement. A widely accepted technique—adopted by IPC—is launch point extrapolation (LPE). This fits a line to the TDR trace and projects it back to the start of the test coupon—the launch point—where the probe and test coupon con- nect (Figure 1). Why not just test at the launch point? TDR testers used for impedance measurement look at the ratio of voltage reflected from the test trace in comparison with a calibrated 50-ohm transmission line standard. At the launch point, the reflection is masked by signal aber- rations caused by the interconnect itself. For this reason, test systems make the measure- ment further down the line over a stable sec- tion to minimize the errors introduced by aber- rations at the launch. With line widths of four mils and above, the DC resistance in the trace is so small that the trace remains flat. As traces get progressively narrower (and with thin copper), the trace will show more and more slope, introducing an error into the characteristic impedance mea- surement. LPE is a proven technique to remove this artifact. Why is the DC resistance ignored? It should not be ignored, but it is a different specifica- tion from the characteristic impedance, and the two should not be lumped together. To think of this in another way, imagine a reel of coaxial cable of 50- or 75-ohm characteristic impedance with a DC resistance of one ohm per meter. Would you say the 50-ohm cable was 60 ohms if you used 10 meters? No! the cable has a 50-ohm characteristic impedance, and the resistance per meter is a separate specification. The same is true for PCB traces. Some PCB fabricators misunderstand this and lump the two specifications together and then try to goal-seek the Dk in a field solver to achieve a correlation between measured and modeled values. This can lead to some very odd results. If the traces are very narrow, solving for Dk Figure 1: Launch point extrapolation.