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82 DESIGN007 MAGAZINE I DECEMBER 2020 tance, the less voltage it can accept before it is fully charged. This relates to the frequency of the spike pulses on the power plane. Small, faster (high-frequency) pulses affect- ing and creating the noise on the power planes are better absorbed by a small capacitor, such as 200–1000 pF. Larger, lower frequency bumps and spikes from big chips and driver transis- tors may need larger 0.1–1-nf sized capacitors. Big, very low-frequency pulses, such as power line ripple, are handled by larger capacitors in the 100-mF size. The capacitor size is its ability to absorb and release energy and is rated in farads. One pF (picofarad) is 10 -12 farads, nanofarads (nF) is 10 -9 farads, and a millifarad (mF) is 10 -6 farads. A small AA-sized battery would be equivalent to a few farads in its ability to absorb and fill in power spikes. As we are trying to reduce the faster noise spikes from switching in the chips, we require the smaller 0.001–0.01-nF sized capaci- tors. To put the discrete little capacitors at every point needed to absorb chips' pulses would mean mounting hundreds or possibly thou- sands of small bypass capacitors all over the PCB. These capacitors cost money to put on and QA after assembly, as well as using up valu- able PCB real estate. We have a few choices in embedding capacitance in the power/ground plane, and each has its own good and bad points. The first is the use of additive films, which have capacitance; they can be imaged and etched. FaradFlex MC25ST, 3M, and DuPont HK04 are some of the most used. A second option is the use of resin-coated copper, such as the RTFoil, or flipped double-treated foil. The thinner laminate layer creates a higher capacitance. The capacitance film applied to the power plane has a very high Dk, which enables higher and better capacitance ratings but still only in the pF range. Remember that Df is a rating of how well two parallel copper conductors separated by a dielectric retain voltage (i.e., its loss value). Thin 2-mil polyimide films have a further advantage of being lower loss than typical FR-4. The Df of flex PI material is 0.002. The Dk factors of 3.2 and the Df loss factor tells us how fast the stored electrons are leaked off. The high loss Df of FR-4 (0.012) is not great for capacitors, as they leak voltage so quickly as to be more of an absorber than a battery. We call that type of capacitor a snubber. The most used method to create capaci- tance between the power and ground plane is to use a very thin layer of FR-4 or flex PI dielectric between the copper layers. The capacitor is made by putting a dielectric (insu- lator) between two parallel conductors. That is exactly what we have in the normal multi- layer ground/power plane core. To make the capacitance large enough to effectively remove the spikes and pulses, we need to increase the capacitance over what is obtained using a typi- cal 5-mil FR-4 or PI core. To increase capacitance, we have three variables: area, which is predefined by the size of the PCB; increase Dk, which is defined by the laminate used (i.e., FR-4 prepreg at 4.2 Dk, and PI has a Dk of 3.2); or we decrease the distance between the two parallel con- ductive plates (i.e., thinner laminate between planes). The easiest to implement is to decrease the spacing between the power and ground cop- per planes while maintaining reliability and voltage ratings. A 2-mil FR-4 core between two copper conductors has a capacitance of 50–250 pF per square inch. There have been many patents over the years pertaining to different applications of this technology; however, most have expired. Presently, there are quite a few We have a few choices in embedding capacitance in the power/ground plane, and each has its own good and bad points.

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