Issue link: https://iconnect007.uberflip.com/i/1327102
JANUARY 2021 I DESIGN007 MAGAZINE 17 6) Non-conductive epoxy-filled vias with Cu cap plates: add 0.5 mil to outer layer space—difficult for <0.5 mm pitch BGAs 7) Controlled impedance lines: a. Increase/decrease with dielectric thickness b. Become very small for small microvia dielectrics, so watch factory minimum line etch capabilities when <3.5 mil. But watch aspect ratio on the microvia when increasing the dielectric to increase the linewidths c. Decrease with increased ohms 8) Minimum drill hole wall to different net Cu (drill-to-Cu) = 8 mil, (Figure 4) the sum of the following: a. Imaging: front-to-back = +/- 0.002" (50 µm) b. Lamination: layer-to-layer registration = +/- 0.003" (75 µm) c. Drill: drill tolerance = +/- 0.003" (75 µm) Let's face it: when well-informed customers are creating designs in accordance with stan- dard guidelines from the fabricators, they're going to have high yields and be easier to run through our shops. And with higher yields, they're going to be more cost-competitive, and they will be less prone to failures. It makes all of our jobs easier, which is why we invest in "training" our customers. Shaughnessy: But things go badly sometimes, and you have some great horror stories that you share with your class. Ellis: One of the designs I'd been asked to review for quote was from a super-nice inde- pendent designer, and it was a medical appli- cation. He had used the component manufac- turers' reference designs off the two 0.5 mm (19.6 mil) pitch BGAs in the schematic. Both designs specified 5-mil vias and 9-mil pads through all six layers, a blatant violation of pad diameter for a mechanically drilled PTH. Luckily, Asia suppliers had already no-bid the job, so I didn't have to be the one to drop the "your design can't be fabricated in any vol- ume" bomb. This one was actually designed as a through- hole design when it really should have been a laser microvia board with a different stackup. Luckily, we were able to fix the design by adding one lamination cycle for microvias on L1–L2 and L2–L3 to the stackup and re-routing some circuitry to achieve what we needed to make it manufacturable. Unfortunately, one of the things that I some- times worry about is when the semiconduc- tor manufacturers supply reference designs they have only used with their local, quick- turn fabricators. Since they haven't designed those for volume production, their customers can get into a bit of a wicket when they try to transfer those often-tested and approved designs. Happy Holden: Yes. Don't talk to us about app notes (laughs). We went through that dis- cussion with the June 2020 issue of Design007 Magazine. Figure 4: Drill-to-Cu minimum of 8 mils.