Issue link: https://iconnect007.uberflip.com/i/1327102
18 DESIGN007 MAGAZINE I JANUARY 2021 Ellis: Absolutely, Happy. Some of the most difficult designs that I see are reference designs from semiconductor customers. We just had another one recently from one of my automotive customers. They used one of their offshore divisions to design a respin of a board that the original designer and I had spent a lot of time on together. It had two high-pin-count 0.65 millimeter-pitch BGAs. They designed them as through-holes, which violates 8-mil drill-to-copper. When it came across my desk, it was being manufac- tured locally at TTM in San Jose, with a 6-mil drill that we don't normally use in China, and my gut just caved, because I'm thinking, "Did I actually lead them into a design like that?" When I brought it up, the design engineer said, "No, Julie, we inherited this one, where the 0.65-mm BGAs were added; we know we need to redesign it." So now we're working on the redesign for volume production that is also high reliability for automotive. In this case, a 0.65-mm pitch BGA using an 8-mil drill hole violates guidelines for 8 mil minimum drill-to- copper. We need to be careful of high-volume designs in China. We will be able to meet the 8 mils through very clever re-routing and off- setting via pads. Shaughnessy: How do you go about navigat- ing this, if you're having your prototype built here, and then they want to build it offshore for volume? I mean, it seems like a delicate kind of dance. Ellis: Oh, it's so scary. There's nothing worse than having to call a designer and say, "Hey, I'm having problems with this finished design, with this stackup, because we can't fabricate it in Asia." But how would a design engineer who has expertise in electronics design know all of this? They can't know everything that I know. I've been doing this for 30 years, which is why they should contact us at the start of their project. Shaughnessy: What are some of the other more common mistakes that you keep seeing? Ellis: A big one is always VIPPO, via-in-pad plated over, when we have non-conductive epoxy-filled holes in a through-hole board with semiconductor or passive components- pads that have vias in them. For the assem- bler to effectively solder those and not have all the solder flow through the holes, we need to fill those with non-conductive epoxy and then Cu plate them, so the pad, even though it has a hole in it, just looks like a rectangular pad that the assembler can solder to without solder going down through the hole. The via-in-pad plated-over process takes extra process steps, so it's significantly more expensive and it also adds plating to the outer layers of the circuit board; when we add the non-conductive epoxy fill, we need at least 0.5 mil more spacing between the fine lines. We also need to recalculate controlled impedance line widths, which become slightly smaller as the Cu thickness increases. Circuit board design engineers don't always think of the ramifications of via-in-pad and how that's going to affect etching or assembly. Richard Dang: Aspect ratio for microvias is another one. I've seen designers come to us with a stackup on their fab drawing, they're specifying dielec- trics, and then they put a microvia in there and they're specifying the microvia size. We see that sometimes designers might not understand that there's an aspect ratio of <0.75: 1 that we have to comply with in order to successfully plate that via. Any time there are microvias, it limits the dielectric thickness between those lay- ers, which will result in small-modelled line widths for your impedances. Your trace and space are also limited by the distance between your microvia pads. A final issue with microvia layers is that dif- ferent factories have different plating capabili- ties, so the resulting plated layers may differ in nominal Cu thickness by 0.2–0.3mil when Richard Dang