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JANUARY 2021 I DESIGN007 MAGAZINE 57 layer is controlled, as attempting to emulate a thin dielectric with prepreg between cores or foil internally for a blind scenario means you will have to consider the additional blind plate- up. This is usually a typical value of 1 addi- tional mil of plating, reducing the thin prepreg dielectric even further and setting yourself up for high resistance shorts and an impedance mismatch. These three things should be considered if you don't want to pay more, increase your lead time, or live with a higher impedance toler- ance. And you'll be able to send your design to just about any fabricator. Conclusion These are the things on a short list of what every stackup should have. I hope this has helped. As usual, if you would like to comment on this column, please do; I greatly appreciate the feedback. I can be contacted at markt@ with your questions and comments, and, as always, thanks for reading! DESIGN007 Mark Thompson, CID+, is a senior PCB technologist at Monsoon Solu- tions Inc. To read past columns or contact Thompson, click here. Thomp- son is also the author of The Printed Circuit Designer's Guide to… Produc- ing the Perfect Data Package. Visit to download this book and other free, educational titles. reason not to do this in my second point later.) Having said that, we see many high-speed and RF designs where this is a negative. Having any via stub can be an issue. Second, avoid having signal integrity needs such as controlled impedances on a blind plate-up layer if you want to be able to send the job to any fab shop. Many fabricators pro- cess a blind or buried via scenario where they laminate the blind or burieds and then drill the scenario instead of doing controlled depth type drilling to drill said scenario after final lam. This means the layers are typically imaged and plated for the termination layer, such as a layer 2 in a blind 1-2 or layer 3 of a blind 1-3 after they have imaged/plated then laminated the blinds in the first cycle press. Since this plate-up can have some slight cop- per thickness deviations after plate due to the plating process variable, they ask that you do not have the blind plate-up layer 2 or the layer 3 for an impedance layer in such a scenario as the ones described previously. If this cannot be avoided, and a controlled impedance layer must reside on a blind plate-up layer, they may ask for a higher tolerance for the impedance, such as ±15%. Third, having a controlled impedance layer on a blind plate-up layer means that controlled dielectrics as the interface where the blind via controlled impedance resides requires a spe- cific dielectric to achieve said impedances. This is where it gets tricky if the termination

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