Issue link: https://iconnect007.uberflip.com/i/1327102
JANUARY 2021 I DESIGN007 MAGAZINE 55 Controlled Impedances Next, I'm going to cover controlled imped- ances (Figure 1 and Table 1). As I have said in numerous columns, first, consult your chosen fabricator to have them assist in specifying the trace widths, spaces, and dielectrics for various impedances. This ensures you won't have to rip up and re-route your impedance tracks and potentially your component placement. I realize many folks do their own calculations, but as I have said before, as a designer, all you have to do is to get within 10% of your precalculations, and the fabricator will take it the rest of the way to get even closer to your desired impedances. Simply call out all the impedances that reside on each layer. If you use a template for this description, that is fine, but make some men- tion if they don't all reside on the called out layers. As a former fabricator, I understood that they may not exist on the design today but may exist on the design at some point in the future. Thus, when I corresponded with the customers, I would simply say we have calcu- lated for them all but have only included cal- culations that reside on the design as it exists. Be sure to add a tolerance for the impedances, wide traces, such as CPWGs, on surface layers, which can have as little as ±5%. But thinner tracks for single-ended and differential pairs should have a larger tolerance like ±10%. If the part has impedances that reside on a blind plate-up layer, the fabricator may even ask for ±15%. Lastly, layer configurations must match the description for both the layer names and the stackup. Any mismatch can cause a delay in your project. Make sure the layer names are also in sequence. For example, a 10-layer board should have layers 1–10 in sequence, not layer 1, 3, 5, and then back to layer 2, 4, etc. This could cause a serious stackup error at fabrication. Likewise, as I said before, the layer names should be the same in the image data and the stackup. Some mismatches are tolerated and understood, such as calling out a PWR plane on the stackup and calling the actual layer +5V. This should be understood by the fabri- cator, but if the names aren't even close, you should expect a phone call or email from your chosen fabricator to clarify. Figure 1: Typical 10-layer stackup. Table 1: Typical impedance chart.