Issue link: https://iconnect007.uberflip.com/i/1355791
86 I-CONNECT007 I REAL TIME WITH... IPC APEX EXPO 2021 SHOW & TELL MAGAZINE technology for their vertical integration strategies. Our own Pete Starkey has detailed that for you here. Diane Maceri, supply chain director, Schweitzer Engi- neering Laboratories, Inc., and Jessi Hall, senior director for vertical integration, Schweitzer Engineer- ing Laboratories, Inc., provided details of the alternatives, and pluses and minuses of going into PCB fabrication. Jeff Leblanc, director of operations for plating fabrication, Vicor Corporation, also detailed their analysis of future options and how they decided to add a modified PCB fabrication facility to their new expansions. Joe O'Neil, CEO, Green Circuits, presented "Chal- lenges and Changes." Joe provided the wrap-up for the day by discussing COVID, market and technology. Stan- dardization is key, niches can be a growth area, and vertical integration is back on the agenda. Technical Track: PCB Fabrication and Materials Tech Sessions SO2-1: Mike Vinson, Averatek, "Semi-Addi- tive PCB Processing: Process, Reliability Test- ing and Applications." Mike provided an over- view of semi-additive PCB processes for ultra- high-density PCBs of 15 microns feature sizes and below. e A-SAP process is a Liquid Metal Ink TM , a few nanometers-thick palladium coat- ing that allows a thin, uniform, and dense elec- troless deposit. It is capable of <15-micron t/s capability with suitable photolithography and etching. Mike provided the process flow, exam- ples of finished geometries and applications that allow use of much smaller packages and reduc- ing layer count. Reliability has shown improve- ments to microvia metallization and high-aspect through-holes. Also presented was RF and SI analysis for high-frequency performance. SO2-2: Manoj Kakade, et all, pSEMI Corp., "ermal Improvement in 3D Embedded Module Using Copper Bar Vias." Manoj dis- cussed the use of copper bar vias in substrates to improve thermal performance. e appli- cation is intended for embedded component integrated into modules. Aer introducing the process, a thorough thermal analysis was dis- cussed including the simulation using Ansys FEM tools. Results indicate that bar vias have lowered Tj by 10°C. S O 5 - 1 : G e r r y Pa r t i da , Summit Interconnect, "Micro- via Weak Interfacial Frac- ture of Microvia Designs- Comparing the Reliability of Graphite-based Direct Met- allization and Conventional Electroless Copper." Summit Interconnect and RBP Chemical Technology conducted a joint project to provide additional insight into the weak interface defect in stacked HDI microvias by processing in either graph- ite-based direct plate or conventional electro- less copper on a specially designed test vehicle. e test vehicle (IPC D coupon) had 3-, 4-, 5-, 6- and 8-mil via, and blind vias on two differ- ent dielectric thicknesses. All were tested to IPC-TM-650 method 2.6.27B and OM Testing. Results indicate that DM process performed equal to or better than conventional electroless copper. e paper provided detailed reliability performance. SO5-2: Jer r y Mager a, Mo toro la So lut ions, " The Comp lete Path to L ea st Resistance Investigating the Source of the Weak Micro- via Interface." Jerry was one of the first to discover the "Weak Microvia Interface" and report on it. He successfully created a test that is now an IPC Test Standard and has done extensive experimentation looking for the root causes. is is a long and detailed paper on the experimentation and results for the last two Alex Stepinski Joe O'Neil Gerry Partida Jerry Magera