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12 DESIGN007 MAGAZINE I MAY 2021 Feature Interview The I-Connect007 Editorial Team Longtime signal integrity experts Rick Hart- ley and Barry Olney join the I-Connect007 Editorial Team for a discussion around DDR and the complications board designers inevita- bly face when they design for DDR. If, as Rick and Barry explain, the DDR design process is not that much more complicated than that of a typical high-speed board, why does DDR cause design engineers so much grief ? Much of this comes down to following the process, running simulation, and not relying on refer- ence designs. Andy Shaughnessy: I thought maybe one of you could explain why DDR is used so oen. What is the advantage of using DDR? Barry Olney: It's the fastest technology we have for memory. With each new version there is a dramatic increase in device data rates and bandwidth; for instance, DDR4 has a maxi- mum data rate of 3200 MT/s whereas DDR5 peaks at 6400 MT/s. PCB Design Challenges: Designing With DDR Rick Hartley: I have not used DDR5, but it's not just double data right now; it's quadruple data. Olney: Yes, DDR5 has only recently come out. A few of the chip manufacturers in Taiwan have it, but I have not seen it myself yet, so I'm looking forward to it. Shaughnessy: What does this look like? What does this entail? When someone says, "We've got a design for this DDR," what are we talking about? Is this a physical thing? Hartley: Like any bus technology it has data, address, clocks, control lines, it has all the things that most bus technologies have. It's source-synchronous clocking, meaning that the clock is launched with signals so you're not launching a clock and then depending on the signals to arrive at the receiver within a given timeframe. You launch all of them together and if all the data, for example, is set up within a certain timeframe relative to the clock/strobe, everything functions as it should. And the same is true for the clocks of the address. It is source-synchronous, which makes it a much, I

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