Issue link: https://iconnect007.uberflip.com/i/1369942
14 DESIGN007 MAGAZINE I MAY 2021 think, easier technology to use. What are your thoughts, Barry? Olney: It is easier to use. Especially with the DDR3, DDR4, and DDR5, now you have the write leveling which synchronizes the clocks to the address, command, and control lines. You must realize that with DDR, there are two sets of clocks. ere is the main clock of the two, and there are also the strobes that trig- ger the data capture. Basically, the clock and strobe must be at the longest delay of all sig- nals because the address and data must settle before the data is captured. Hartley: e key is to route the strobe to the longest so that it has the greatest delay and arrives last. Olney: Exactly, and that's what a lot of people don't do. ey have the strobe arriving first and then the data last, and you get all the reflec- tions and noise. You don't know whether it's going to capture the correct data. Hartley: e first time I did a DDR2 design was at L3 in 2012, and the next one we did was also DDR2 in 2014. One of our engineers did a tim- ing analysis of the design in 2014. He came up with a number that nobody believed. Every- body in engineering said, "Oh, this can't be right, because all the app notes say that DDR timing is so critical." We came up with a num- ber that said, for example, that the address line only needed to be ±125 mils from some opti- mal length, which is basically ± 3 mm. Every- body said, "is can't be right." Yet shortly aer that, I ran into a note that I found from Keysight Technology, written by an engineer named Chang Fei Yee, who wrote: "Maximum DDR2 skew of trace length to meet timing margin. In order to be compliant with the JEDEC specification, the maximum skew among all signals shall be less than ±2.5% of the clock period drew in by the memory con- troller. All signals of the SDRAM are directly or indirectly referenced to the clock, for example in normal FR-4 material with a dielectric constant of approximately four, a differential clock-rate of 1.2GHz, the maximum skew shall be ±125 mils, or ± 3 mm." is is precisely the number we came up with, even though half the engineers in our department said it couldn't be right. I inten- tionally mismatched the length of some of these lines just to keep them within that quar- ter of an inch distance from one another, and the thing worked perfectly. at was when I first realized how noncritical this really is. Olney: I have a table on that, Rick. For 166 MHz, the interconnect margin is 155 picosec- onds. Hartley: Yes, which is huge! Olney: at relates to about 75 mils. Hartley: I know, it's crazy. And people route these things within ±5 mils or ± 0.1 mm. Barry Olney