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32 DESIGN007 MAGAZINE I MAY 2021 age regulator module on the PC board) to the switching IC as fast as possible. When the output stage of a digital IC switches from high to low or from low to high, there is a period when both output devices are partially turned on. is causes a large cur- rent pulse between the supply rail and power return pin of the IC. is "shoot through" cur- rent pulse tends to lower the supply voltage, causing what's known as simultaneous switch- ing noise (SSN) on the power rail. is SSN tends to propagate throughout the PCB. A well designed PDN minimizes this SSN. Capacitors, in the form of bulk, decoupling, and board capacitance, are used to store enough energy to overcome the tendency of the power rail voltage to decrease. Figure 13 shows a typical circuit model of a PDN with the power source on the le, supplying energy to the IC on the right. In between, we have a series of energy storage capacitors and transmission lines (PC traces). Unfortu- nately, it takes significant time to transfer the required energy from the power source to the IC. It has been shown that it takes about 600 ps to transfer an amp of current across 1/16th inch of die bonds. [11] at's why it's especially important to keep PDNs short and direct as possible. Ideally, the total energy demand will be met by the "on-chip" capacitors, if any, plus the energy stored in the power plane capacitance. However, these are seldom enough storage, so we depend a lot on nearby decoupling capaci- tors to supply the remaining energy demand. It is critical for the decoupling capacitors to have as little series inductance (in the form of internal inductance and trace inductance) as possible. e greater this series inductance, the harder it is to supply the required energy to the load and SSN results with related noise coupling throughout the PCB. Assuming the decoupling and any built-in capacitance of the PCB can supply the energy needs, then the job of the bulk capacitor is to "recharge" the energy of the downstream capacitors in between switching transients. For the fastest recharge times, the PDN must be in the form of low impedance transmission lines. e bulk capacitors (4.7-10 μF, typ.) are usually placed near the power input connec- tor and the decoupling capacitors (1 to 10 nF, typ.) nearest the noisiest switching devices. To achieve the lowest series inductance, all decou- pling capacitors should be mounted as close to the IC to be decoupled as possible and right over (or close to) the connecting vias. Multiple vias should be used for each end of the capaci- tor to further reduce series inductance. More on PDN design may be found in the reference section. [8-10] Figure 13: A typical circuit model of a power distribution network (PDN).