Issue link: https://iconnect007.uberflip.com/i/1369942
MAY 2021 I DESIGN007 MAGAZINE 19 3.3-volt lines, which will severely increase crosstalk into the lower voltage line. Olney: e last design I did had 35 different power supplies. Hartley: Now that becomes tougher. Olney: How do you put 35 different copper pours in? e main processor BGA has four or five different supplies that must connect to other circuitry; that blocks your routing chan- nels and makes it really challenging: "We'll fit them in here or there on plane or signal layers." But when you start routing it, pushing traces around and trying to get around these copper pours, it's very difficult. Hartley: It is very challenging, I agree. Olney: One of the nice things about DDR is that it's source-synchronous, and so you can route it to a 4-mil trace with 4-mil spacing. You don't have to worry about crosstalk because the data and address arrive at the memory chips and it has time to settle before the clock and strobes come along and capture that data. Providing the clock is a little bit longer, it all works with- out crosstalk and reflections. You just don't want to get the data and address mixed up. Shaughnessy: Barry, in your columns you talk about the benefits of using a router for DDR3 and that designers typically don't like auto- routers, but you said they can be very useful here and you can drive the router with the schematic. Olney: Absolutely. If you set up the constraints properly in the schematic then you can drive the router from the schematic, which I do. First, when you select a chip—maybe from the main processor or a part of that, mainly just the memory bus—you fan out from that, gener- ally from the top layer to internal layers so you don't have to route on the external microstrip layer, which can radiate a lot of EM; it's also faster speed so you don't have to worry about the difference in propagation delay, between different layers. Stripline traces also have less crosstalk which means you can route in closer proximity. I fan out first, and then I'll select the first data bus going to the first memory; I will route that with the router, so I route it bit by bit and as I do it, I clean it up. If it doesn't do it quite perfectly, I can push and shove it around and get the signals almost right. Once you've basically routed it and you've made sure you've got a little bit of room for ser- pentines, then you can apply the fine tuning, the auto-tuning of the routes. Cadence and Altium can route to delay, so you don't route to length anymore. Length and delay are two totally dif- ferent things, depending on which layer you're on, so if you're routing to delay, you're getting the exact numbers, the exact flight time, to every chip in comparative flight time. Shaughnessy: Do designers run into trouble with the other serial links like PCI Express? Or is that just a different animal? Olney: Generally, PCI Express goes to a con- nector, so they're spread out to start with and you just follow the pattern and basically route them in order. You can have them tightly together, and you must in most cases. Hartley: It is a different animal, and it's like eth- ernet or any of those things; they generally go to a connector. Shaughnessy: But DDR can be employed any- where. at's the beauty of it, I guess. Olney: It can also go to a connector. You may have onboard memory, or if you could have SODIMMs, for instance. When you're rout- ing to SODIMMs, it's quite a different strategy than routing to onboard memory. In onboard memory, you generally don't have series ter- minators on your data. With plugin memory,