Issue link: https://iconnect007.uberflip.com/i/1381013
50 DESIGN007 MAGAZINE I JUNE 2021 argument is to put the AC coupling capaci- tor close to the receiver and you'll be good, since all of the reflections will be smaller due to transmission line attenuation. is repre- sents a time domain view of the world. e second argument is that for most passive interconnects, S-parameters are reciprocal (S21 = S12). Under this pretense, for a par- ticular topology, as long as the distance from the endpoints to the AC coupling capacitor is the same, it does not matter if you place the capacitor at the receiver or driver, because the results will be identical. is represents a fre- quency domain view of the world. However, in practice it's slightly arbitrary. Oen it's defined by a standard and the capacitors are specified on one end or the other end or occasionally on both ends. For instance, PCIe (PCI Express) specifies the AC coupling caps on the TX side, as there are methods it uses for detecting if a downstream device is connected that depends on that particular AC coupling configuration. e other issue with routing serial links, on outer microstrip layers, is the solder mask coat- ing. Having solder mask on microstrip traces will make them more unpredictable since it's difficult to control the thickness of coating on the top of traces and in the valley between them. So, if the solder mask is removed around the traces, it can improve the channel perfor- mance. However, there are a few down sides to this: 1. Depending on the substrate used, you might also find that humidity can enter the substrate surrounding the traces and may impact the impedance (solder mask is a very good water seal, so you will usually not see this effect with covered traces). 2. Also, if you are using ENIG plating, be careful with how thick the gold and nickel layers are, since you might end up with narrowband resonance. At approximately 2.7 GHz, the resonant behavior of the nickel component in ENIG increases insertion loss. is resonance is attributed to the ferromagnetic properties of the nickel layer. It is therefore wise to avoid using full body ENIG coating of microstrip traces at high frequencies. Consequently, solder mask over bare copper (SMOBC) processing should be considered for all high-speed designs. However, solder mask only impacts signal integrity above 12 Gbps. Alternatively, to avoid the solder mask issue altogether, one could run differential serial links on the second layer of a dual build-up microstrip construction. is stabilizes the sig- nal as it has a layer of prepreg over the traces. However, it will have impedance discontinui- ties due to the blind vias between layers 1 and 2 but this is practicable negligible. When high-speed differential serial signals travel between boards, the destination loca- tion could have a different level on its ground. So, the transmitter and receiver could have dif- ferent reference levels. A different ground level would cause the signal to appear to have a level shi that might make its level out of range for the receiver. AC coupling allows the receiver to change (bias) the signal reference levels to be compatible with the receiver's input levels. However, PCB designers must be able to iden- tify any discontinuities in the high-speed chan- nel and mitigate their impact to improve the performance of the signal transmission. Key Points • e simplest method of transferring data through the I/O of ICs is to directly connect the data path from one IC to the next in parallel. • DDR memory devices take advantage of the fast data transfer rates of the parallel bus. • A parallel clock SERDES combo is normally used to serialize wide data- address-control parallel buses such as PCI. • Parallel communication is intrinsically faster than serial.