Issue link: https://iconnect007.uberflip.com/i/1381013
JUNE 2021 I DESIGN007 MAGAZINE 69 reduce layer count, reduce lamination cycles, and reduce the number of microvia layers needed, which all increase yield and overall reliability. What aspect of these new PCB fab- rication capabilities is most valuable to you? Chester: I think all designers are going to be excited with the ability to access some of these benefits. For me personally I am excited about the ability to breakout of the µBGA part without needing to do other HDI design strategies. Dunn: You are currently working on a proj- ect that involves redesigning an Altium refer- ence design, applying 25-micron trace/space where it makes sense. Can you tell us about the project? Chester: To get a better understanding of some of the requirements and difficulties a designer would need to design an SAP product, I am using an existing Altium DDR4 SODIMM design to reimagine it utilizing SAP. is is resulting in some promising improvements with respect to layer reduction and it also has reduced the overall complexity of designing a DDR4 fly-by architecture. As with any engi- neering process, there are some assumptions that have been made with respect to the design as we are still in the early days of SAP, so this is intended as a learning and educational piece with an understanding that it may not be func- tional. However, as I said, it is more about the experience and getting that key information on how to implement SAP into a design and what improvements come out of it. e key in this situation is having an existing design that we can refer to and compare the changes once we complete the design. Dunn: I am looking forward to those results. Working with something new can be exciting and just a little intimidating. In navigating the learning curve, do you see any challenges for designing with this new technology in mind? Chester: I think that there are some chal- lenges that will need to be overcome. Due to the changes in trace size and with respect to how new this process is, the impedance and the field theory around using this in a design is still being developed. e SAP process means we are shiing away from planar coupling of traces and starting to deal with broadside cou- pling and the requirements for co-planar wave guides. Currently there is no proper way to cal- culate what this is going to do at such a small scale, which could cause all sorts of design and signal integrity issues. Dunn: Tomas, as we wrap up, what advice would you give to PCB designers who are just hearing about the opportunity to work with fabricators that can now offer these fine feature sizes? Chester: Get in touch with your fabricator as early as possible and make sure you discuss this with them. ey will have all kinds of insight on what to do and having them review your design as you progress will increase the chances of a Revision A success. ey will also be able to give you additional details of their capabilities and any issue areas they have encountered on other previous designs. Dunn: ank you so much for talking with me today. DESIGN007 Tara Dunn is the vice president of marketing and business development for Averatek. To read past columns or contact Dunn, click here. I think all designers are going to be excited with the ability to access some of these benefits.