Issue link: https://iconnect007.uberflip.com/i/1383248
52 PCB007 MAGAZINE I JUNE 2021 e versatility and design flexibility are sub- stantial advantages of the TLPS paste via pro- cess; however, absence from common indus- try design tools presents a challenge in explor- ing potential stack-ups. Partnerships are being formed to create design patches that enable de- signers to explore constructions that contain paste vias alongside conventional techniques. Performance of TLPS Z-axis Interconnect vs. Conventional Fabrication Methods Performance of TLPS paste Z-axis intercon- nects relative to plated interconnects is obvi- ously a topic of interest. An early test vehicle by i3 Electronics investigated the relative per- formance of purely PTH constructions and those broken by a layer of TLPS vias. S-pa- rameter measurements were made on a net that contained only PTH versus one that con- tained four sintered interconnects. Figure 9 demonstrates that the use of sintered intercon- nects connecting PTH bearing subs in place of a continuous PTH does not significantly de- grade the signal performance. Below 10 GHz the difference between a copper barrel struc- ture and a sintered via structure is negligible, and above 10 GHz there is only a slight degra- dation due to the additional via length. Over- all, the performance is similar to a solid cop- per barrel. [3] Full-Z test vehicles in which the copper in- terconnects were entirely replaced with TLPS vias layers also demonstrated equivalent per- formance to the plated copper interconnect control in third party testing. [4,5] In recent work to support the growing high frequency market, a dedicated test coupon was designed by Insulectro [6] to test the sig- nal integrity and current-carrying capability performance of various TLPS paste via struc- tures relative to conventional PTH and plat- ed-microvia fabrication methods. e cou- pon contains 10 nets including a copper mi- crostrip baseline, and nine comparison nets for signal integrity performance and current- carrying capacity. e coupon design is de- tailed in Figure 10. Figure 10: Dedicated high frequency test coupon for plated copper vs. TLPS paste interconnects. Figure 9: Insertion loss of nets with and without TLPS interconnects. (Source: i3 Electronics)