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18 DESIGN007 MAGAZINE I JULY 2021 Signals pass relatively undistorted along short, coupled serpentine sections, but distortion begins to occur when the parallel trombone length approaches one-third the signal wave- length. Figure 2 depicts a properly routed DDR4 fly-by design using short serpentines. A tight design calls out explicit tolerances on signal timing. e timing requirements for DDR memory are outlined in the JEDEC stan- dards and should be used as a metric for accu- racy. e meandering traces must be com- pacted into an extremely tight space and so one is oen tempted to use any method avail- able to complete the design. e boundary between short and long coupled switchbacks is fuzzy. In general, when the round-trip delay of a heavily coupled switchback far exceeds one-third of the rise time, you get seriously distorted signals; when it's much less than one- third, you get advanced timing—and that's what we typically see. A 1 ns rise time used in an FR-4 dielectric limits the maximum useful coupled switchback length to about 1 inch (2 inches, round trip). A 100 ps rise time limits the maximum coupled switchback length to about 100 mil. In an outer layer microstrip configuration, the mutual capacitive coupling between adja- cent traces is generally weaker than the mutu- ally inductive coupling, driving the FEXT co- efficient negative. However, forward crosstalk does not exist in the stripline configuration. e fine balance between induc- tive and capacitive coupled cross- talk produces almost no observ- able forward crosstalk. Also, the peak amplitude of the crosstalk is considerably reduced. So, all other factors being equal, here is just another good reason why one should always route high-speed signals on the inner layers of a multilayer PCB. Stripline edge- coupled signals can also be placed closer to each other as compared to the microstrip equivalent, which leaves more space for routing and is always welcomed. When selecting a serpentine routing method, one should avoid long, coupled switchbacks as highlighted in violet in Figure 3. is was taken from a DRR4 reference design that I came across recently. Don't try this at home! e dark blue highlighted serpentine has an ideal configuration. Figure 4 plots the comparison of a straight trace vs. a serpentine trace routed on the outer microstrip layer. Green is the driver; red is the straight (reference) trace; and blue is the ser- pentine trace with short, coupled segments. As can clearly be seen, the blue serpentine trace leads the red reference trace by 15 ps despite being the same length. As the trombone par- allel sections increase, so does the velocity of the signal. e dip in the blue serpentine trace (around 5 ns) is the forward crosstalk which would not be present on an inner stripline layer. If the switchback delay is much less than the signal rise time, the NEXT distortion blends into the overall shape of the rising edge. e NEXT distortion for short switchbacks doesn't impact the shape of the rising edge, but it advances the time of arrival. at is, short, cou- pled switchbacks produce smaller delays than the total trace length would indicate. Long, coupled switchbacks also distort the signals and are not recommended. e key is to route the clock and strobes first as straight as pos- Figure 2: DDR4 fly-by routing.