Issue link: https://iconnect007.uberflip.com/i/1391285
28 DESIGN007 MAGAZINE I JULY 2021 Rick Hartley: Copper pours can be a double- edged sword. From a manufacturing point of view, copper pours in unused areas will help balance the construction of the PC board, helping to prevent bow and twist and ensur- ing even copper plating on the outer layer fea- tures (traces, pads, etc.). If the only concern is that of even plating on the outer surfaces, thief copper (in the form of copper dots) can be used instead of copper pours. at said, copper dots do not help with bow and twist caused by uneven copper on inner layers. Talk to your fabricator, who will explain why these statements are generally true and how to best handle your particular designs. Copper pours can have great value to the circuit, but only when implemented correctly. Randomly placing ground pours on all signal layers generally offers no value to the perfor- mance of the circuit, nor do these pours help control EMI. Worse, randomly placed copper pours can cause problems if the segments are not properly attached to a plane with adequate vias to keep copper elements from resonating. Resonating copper elements can cause coupling of energy into other features on the PC board. One technique that can be very helpful is to alternate layers of power and ground in the board stackup. For example, in a six-layer board, with a ground plane on layer 2 and a power plane on layer 5, placing power pours on layers 1 and 3 and placing ground pours on layers 4 and 6 will create a PC board of the fol- lowing arrangement: L1: Signal/Power L2: Ground Plane L3: Signal/Power L4: Ground/Signal L5: Power Plane L6: Ground/Signal e above stackup, due to the added power pours on L1 and L3 and ground pours of L4 and L6, will improve power delivery to ICs on the board. is can and usually will improve both signal integrity and EMI. e EMI improve- ment is not caused by the shielding effect of the copper pours, but rather by the improved power delivery due to lower power bus imped- ance at high frequencies (the harmonics of the square waves). To avoid unwanted resonances with cop- per pours, tie all power pours to the power plane with vias placed every one-tenth wave- length of the max harmonic frequency of the fastest transmission lines in the circuit. Also tie all ground pours to the ground plane every one-tenth wavelength as well. Frequency in GHz=0.5/signal rise time. Is it best practice to flood with copper (tying all areas to GND as needed) all unused portions of all layers? Q